Design Verification Engineer

Intelliswift - An LTTS Company; Austin (TX); On-site; USD 120,000 - 150,000; Full time

Job summary

Intelliswift - An LTTS Company on-site in Austin, TX or Sunnyvale, CA is seeking a senior verification engineer to define and implement IP/SoC verification plans, build verification test benches and drive verification across blocks.

You will collaborate with Design, Model, Emulation and Silicon Validation teams, using SystemVerilog UVM and C/C++ based workflows, Python scripting, and industry tools to achieve first-pass success.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• 5+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification.
• Track record of 'first-pass success' in ASIC development cycles.
• 5+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.
• Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.
• Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.

Responsibilities

• Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification.
• Develop functional tests based on verification test plan.
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
• Debug, root-cause and resolve functional failures in the design, partnering with the Design team.
• Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
• Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.

Skills

SystemVerilog

UVM

C/C++

Python

Test benches

Verification

Education

Bachelor's degree in CS/CE

Tools

Git

Mercurial

SVN

Job description

Full time role with L&T Technology Services

Onsite at Austin, Texas or Sunnyvale, CA

Job Description & Skill Requirement

Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification.

Develop functional tests based on verification test plan.

Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.

Debug, root-cause and resolve functional failures in the design, partnering with the Design team.

Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.

Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.

Minimum Qualifications

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

5+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification.

Track record of 'first-pass success' in ASIC development cycles.

5+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.

Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.

Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.

Preferred Qualifications

Experience in development of UVM based verification environments from scratch.

Experience verifying GPU/CPU designs.

Experience with micro-architectural performance verification.

Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs.

Experience with verification of ARM/RISC-V based sub-systems or SoCs.

Experience with IP or integration verification of high-speed interfaces like PCIe, RoCE, DDR, HBM, Ethernet.

Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation.

Experience working across and building relationships with cross-functional design, model and emulation teams.

Experience with revision control systems like Mercurial(Hg), Git or SVN.