Design Verification Engineer - Internal IP

Etched.ai, Inc.; San Jose (CA); On-site; USD 100,000 - 150,000; Full time

Benefits offered by this job

Medical, dental, and vision packages

$500 monthly credit for waiving medical benefits

Housing subsidy of $2k per month

Relocation support

Wellness benefits

Daily lunch + dinner in office

Job summary

Etched.ai, Inc. is seeking a Design Verification Engineer for their Internal IP DV team in San Jose. This role involves ensuring custom IPs are robust and silicon-ready, developing and maintaining UVM/SystemVerilog testbenches, and collaborating with architects and designers. Candidates should have proficiency with UVM, SystemVerilog, and strong debugging skills. Benefits include medical coverage, a housing subsidy, and daily meals in the office.

Qualifications

• Proficiency with UVM and SystemVerilog.
• Strong debugging and problem‑solving skills for complex digital designs.
• Hands‑on experience verifying datapaths, memory systems, interconnects, or high‑throughput fabrics.

Responsibilities

• Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs.
• Define and execute verification plans covering functional correctness and performance.
• Debug complex datapath and protocol issues in RTL and testbench environments.

Skills

UVM

SystemVerilog

Debugging skills

Problem-solving skills

Knowledge of computer architecture

Tools

Python

Perl

TCL

Job description

Job Summary

We are seeking a Design Verification Engineer to join our Internal IP DV team. You will ensure the custom IPs powering Sohu — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon‑ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware‑software stack.

Key responsibilities

• Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems).

• Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks.

• Debug complex datapath and protocol issues in RTL and testbench environments.

• Work closely with architects and designers to validate functionality and design intent.

• Partner with SW, FW, and emulation teams to ensure end‑to‑end bring‑up and debug coverage.

• Contribute to reusable DV infrastructure, coverage models, and methodology improvements.

You may be a good fit if you have

• Proficiency with UVM and SystemVerilog.

• Strong debugging and problem‑solving skills for complex digital designs.

• Solid knowledge of computer architecture and digital design fundamentals.

• Hands‑on experience verifying datapaths, memory systems, interconnects, or high‑throughput fabrics.

Strong candidates may also have experience with

• Familiarity with SystemVerilog Assertions (SVA) and formal verification techniques.

• Experience verifying systolic arrays, DMA engines, or NoC/AXI protocols.

• Scripting skills (Python/Perl/TCL or similar) for automation, debug and regression flows.

Benefits

• Medical, dental, and vision packages with generous premium coverage

  • $500 per month credit for waiving medical benefits

• Housing subsidy of $2k per month for those living within walking distance of the office

• Relocation support for those moving to San Jose (Santana Row)

• Various wellness benefits covering fitness, mental health, and more

• Daily lunch + dinner in our office