ASIC Senior Verification Engineer

Retym, Inc; Austin (TX); On-site; USD 120,000 - 160,000; Full time

Job summary

Retym, Inc is looking for a Senior Verification Engineer in Austin, Texas to lead complex RTL design verification processes for next-generation high-speed communication technology.

The ideal candidate has over 10 years of verification experience, notably in VLSI verification flows, and will be responsible for developing test bench architectures and mentoring junior engineers. The role demands strong collaboration with design and architecture teams.

Qualifications

• 10+ years of experience in verification.
• Completed 2 or more full block/system verification cycles.
• In-depth knowledge in VLSI verification.

Responsibilities

• Own block/cluster verification from start to finish.
• Lead efforts on test bench architecture and functional coverage.
• Mentor less experienced engineers.

Skills

VLSI verification flow

SystemVerilog

UVM methodology

Ethernet protocols

Mentoring engineers

Job description

For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Senior Verification Engineer to be driving into the complicated RTL design verification activity on various design aspects.

Key Responsibilities

• Ownership of block/cluster verification end to end from scratch.
• Lead efforts of test bench architecture, Vplan definition and functional coverage.
• Work closely with the design, architecture, algo teams and other stakeholders.
• Support other team members and mentor less experienced engineers.

Requirements

• 10+ years of experience – a must
• Performed at last 2 or more full block/system verification cycles.
• In depth knowledge in VLSI verification flow, languages and concepts.
• Experience in data path or data protocols, specifically Ethernet - preferred
• Verification using one of the known methodologies (eRM, UVM).

Additional Responsibilities

• Plan and perform the verification of digital design blocks according to the design specification and interacting with design engineers.
• Build verification environments using SystemVerilog and UVM.
• Identify and write all types of coverage measures for corner-cases.
• Debug the functionality with design engineers.
• Perform coverage collection and follow the metrices to close the full functionality.