Senior Defect Modeling & 3D Packaging Lead

TSMC - Taiwan Semiconductor Manufacturing Company Limited

California

On-site

USD 153,000 - 244,000

Full time

14 days+

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Job summary

TSMC - Taiwan Semiconductor Manufacturing Company Limited in San Jose, CA seeks an experienced engineer to advance defect modeling, testing, and analysis for next‑gen 2.5D/3D packaging. This role emphasizes developing models, running SPICE simulations, and collaborating with design, process, test, and reliability teams to push innovative approaches.

You will contribute to methodologies for defect detection, test strategy optimization, and industry-leading packaging solutions, with visa

Qualifications

Master’s or Ph.D. in Computer Engineering, Semiconductor Physics, or a related field.
15+ years of experience in failure mechanisms, defect physics, testing, or reliability analysis for semiconductor devices (2D/3D).
Proficiency with SPICE simulations, LVS/DRC, and DFT/ATPG; programming/scripting for automation (Python/Perl/C++); AI/ML experience a plus.

Responsibilities

Defect Modeling & Analysis for 2D and 3D structures including TSVs, interconnects, and bonding.
Simulation & ATPG using SPICE tools; develop defect-oriented test patterns.
Testing & probing structures to monitor process variations and enhance yield; collaborate with cross-functional teams.
Research & optimization of defect detection methodologies for chip and package levels; contribute to patents/publications.
Cross-functional collaboration across design, process, and manufacturing teams (approx. 75% research).