Senior Defect Modeling & Testing Architect

TSMC; San Jose (CA); On-site; USD 152,500 - 244,000; Full time

Benefits offered by this job

Market-competitive pay

Comprehensive benefits

Opportunities for development

Job summary

A leading semiconductor foundry in San Jose is seeking an experienced engineer to develop defect modeling methodologies and tools for advanced packaging technologies. This role involves collaboration with design and testing teams and demands over 15 years of experience in semiconductor reliability and defect physics. The position offers a base salary range of $152,500 to $244,000 and a chance to influence industry standards. Join us to shape the future of semiconductor innovation.

Qualifications

• 15+ years of expertise in failure mechanisms or reliability analysis in semiconductor devices.
• Experience with defect physics and testing methodologies.
• Familiarity with AI/ML for defect prediction is a plus.

Responsibilities

• Develop defect models for 2D and 3D semiconductor structures.
• Conduct SPICE simulations and identify failure scenarios.
• Assess probing techniques and their impact on defect detection.

Skills

Defect modeling and analysis

SPICE simulation tools

Programming skills (Python, Perl, C++)

Deep understanding of defect physics

Education

Master’s or Ph.D. in Computer Engineering, Semiconductor Physics, or related field

Tools

HSPICE

PSPICE

Spectre

LVS/DRC tools

Job description

A leading semiconductor foundry in San Jose is seeking an experienced engineer to develop defect modeling methodologies and tools for advanced packaging technologies. This role involves collaboration with design and testing teams and demands over 15 years of experience in semiconductor reliability and defect physics. The position offers a base salary range of $152,500 to $244,000 and a chance to influence industry standards. Join us to shape the future of semiconductor innovation.