Senior DDR5 Firmware Engineer: Init & Margining

Montage Technology, Inc; Johns Creek (GA); Hybrid; USD 140,000 - 180,000; Full time

Job summary

Montage Technologies is expanding in Johns Creek, GA with a hybrid work model and seeks a Senior to Staff level DDR5 firmware engineer. You will develop, debug, and optimize memory initialization, training, and margining across silicon platforms, collaborating with hardware, design, and validation teams to ensure high-performance memory operation from power-on through production.

The role demands hands-on firmware work, C/C++ proficiency, and experience with DDR/DDR5 training, margining, and lab

Qualifications

• Minimum 5 years of embedded firmware experience.
• B.S./M.S. in Electrical Engineering, Computer Engineering, or Computer Science.
• 5–15 years of relevant DDR/DDR5 memory development experience.

Responsibilities

• Develop, debug, and maintain embedded firmware for memory training and margining.
• Implement and optimize memory training and margining algorithms with hardware teams.
• Develop margining sweeps and eye-margin analysis across process, voltage and temperature (PVT).
• Work on signal integrity and equalization techniques to tune link margins for high-speed DDR.
• Support memory initialization, configuration, training, and runtime across platforms.
• Debug hardware/firmware interactions during bring-up and post-silicon validation.
• Create firmware design docs and training/margining algorithm descriptions.

Skills

Embedded firmware

Bare-metal

Low-level APIs

C/C++

Memory subsystems DDR/DDR5

Memory training algorithms

DDR margining

System bring-up

JTAG debugging

Python

Bash

Lab testing

Git

Education

Bachelor/Master in EE/CE/CS

Tools

None

Job description

Montage Technologies is expanding in Johns Creek, GA with a hybrid work model and seeks a Senior to Staff level DDR5 firmware engineer. You will develop, debug, and optimize memory initialization, training, and margining across silicon platforms, collaborating with hardware, design, and validation teams to ensure high-performance memory operation from power-on through production.

The role demands hands-on firmware work, C/C++ proficiency, and experience with DDR/DDR5 training, margining, and lab