Senior Firmware Architect - DDR5 PHY & Silicon Bring-up

Cadence Design Systems; Austin (TX); On-site; USD 110,000 - 170,000; Full time

Job summary

Cadence Design Systems in Austin is seeking a firmware engineer to join the DDR5 PHY IP Front End Design team. You will develop firmware for DDR5 PHY using microcontrollers and C, creating bare-metal APIs and collaborating with hardware designers and memory subsystem architects.

You will also work with verification teams on firmware-hardware co-verification, debug RTL-based simulations, and assist on silicon bring-up boards, contributing to high-speed interfaces and tooling with scripting.

Qualifications

• Experience in bare-metal firmware for high-speed SerDes or memory interface PHY blocks.
• Knowledge of C for embedded software and IDE usage.
• Good knowledge of DDR5 JEDEC and DIMM configurations/specifications.
• Comfortable debugging RTL simulations involving firmware and microcontroller subsystems.

Responsibilities

• Develop firmware for DDR5 PHY using microcontrollers.
• Develop firmware in C with bare-metal APIs on MCUs.
• Collaborate with hardware designers to derive training algorithms and implement them.
• Collaborate with verification team for firmware-hardware co-verification planning.
• Develop and debug firmware in RTL-based hardware simulations (C + Verilog).
• Develop and debug on silicon bring-up boards.

Skills

DDR5 knowledge

Bare-metal firmware

C programming

Scripting TCL/Python

RTL debugging

Silicon bring-up

Tools

Verilog

EDA tools

Job description

Cadence Design Systems in Austin is seeking a firmware engineer to join the DDR5 PHY IP Front End Design team. You will develop firmware for DDR5 PHY using microcontrollers and C, creating bare-metal APIs and collaborating with hardware designers and memory subsystem architects.

You will also work with verification teams on firmware-hardware co-verification, debug RTL-based simulations, and assist on silicon bring-up boards, contributing to high-speed interfaces and tooling with scripting.