Memory Subsystem Validation Engineer - DDR & SI Expert

NVIDIA; Santa Clara (CA); On-site; USD 108,000 - 213,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a hardware engineer to take our GPU memory subsystem from first silicon power-on to production from its memory bring-up to validation. You will plan and perform DDR memory tuning, review designs, and debug issues across silicon, board, and software layers.

The role emphasizes cross-functional collaboration across time zones and a strong EE foundation, with equity and benefits available. This posting reflects an existing vacancy and is based in California.

Qualifications

• BS or MS EE degree with affinity for mixed signal/analog, embedded systems, and digital design (or equivalent experience).
• 2+ years relevant experience.
• Understanding of high speed signal integrity and experience with oscilloscopes.
• Understanding of schematic capture and board design.
• Working knowledge of PC systems, Windows OS, and Linux.
• Excellent understanding of EE fundamentals. Able to break problems down based on first principles.
• Familiar with scripting or programming languages such as C, C++, JAVA, Python, or Perl.
• Possess good collaboration and cross-disciplinary teamwork skills. Comfortable working across time zones.
• Deeply curious about technology and passionate about learning.

Responsibilities

• Planning and performing DDR memory tuning, validation, and feature enablement on NVIDIA products.
• Reviewing silicon design specifications, component datasheets, board schematics, and layout.
• Debug and resolve controller, memory, board, or software/firmware level issues at all stages of the product.
• Refining memory bringup and validation strategy; providing feedback to silicon, board, and software teams.

Education

Electrical Engineering degree (BS or MS)

Tools

C

C++

JAVA

Python

Perl

Job description

NVIDIA is seeking a hardware engineer to take our GPU memory subsystem from first silicon power-on to production from its memory bring-up to validation. You will plan and perform DDR memory tuning, review designs, and debug issues across silicon, board, and software layers.

The role emphasizes cross-functional collaboration across time zones and a strong EE foundation, with equity and benefits available. This posting reflects an existing vacancy and is based in California.