Senior Staff Firmware Engineer

Montage Technology, Inc; Johns Creek (GA); Hybrid; USD 140,000 - 180,000; Full time

Job summary

Montage Technologies is expanding in Johns Creek, GA with a hybrid work model and seeks a Senior to Staff level DDR5 firmware engineer. You will develop, debug, and optimize memory initialization, training, and margining across silicon platforms, collaborating with hardware, design, and validation teams to ensure high-performance memory operation from power-on through production.

The role demands hands-on firmware work, C/C++ proficiency, and experience with DDR/DDR5 training, margining, and lab

Qualifications

• Minimum 5 years of embedded firmware experience.
• B.S./M.S. in Electrical Engineering, Computer Engineering, or Computer Science.
• 5–15 years of relevant DDR/DDR5 memory development experience.

Responsibilities

• Develop, debug, and maintain embedded firmware for memory training and margining.
• Implement and optimize memory training and margining algorithms with hardware teams.
• Develop margining sweeps and eye-margin analysis across process, voltage and temperature (PVT).
• Work on signal integrity and equalization techniques to tune link margins for high-speed DDR.
• Support memory initialization, configuration, training, and runtime across platforms.
• Debug hardware/firmware interactions during bring-up and post-silicon validation.
• Create firmware design docs and training/margining algorithm descriptions.

Skills

Embedded firmware

Bare-metal

Low-level APIs

C/C++

Memory subsystems DDR/DDR5

Memory training algorithms

DDR margining

System bring-up

JTAG debugging

Python

Bash

Lab testing

Git

Education

Bachelor/Master in EE/CE/CS

Tools

None

Job description

Job Title: DDR5 Firmware Initialization and Margining Engineer - Senior to Staff Level

About Us

Montage Technologies is opening a new U.S. location in the Johns Creek, GA area offering a Hybrid work environment. We are an emerging semiconductor company specializing in enterprise class memory products. There will be many hands-on learning experiences with significant program ownership and career growth.

Founded in 2004, Montage Technology is a leading IC design company dedicated to providing high-performance, low-power IC solutions for cloud computing and data center markets. Montage Technology provides industry leading DDR2 to DDR5 memory interface products for the demanding cloud computing and data center markets. Our robust product portfolio includes the critical components required by the memory modules, such as Registering Clock Driver (RCD), Data Buffer (DB), SPD EEPROM with Hub (SPD Hub), Temperature Sensor (TS) and Power Management IC (PMIC). Compliant with JEDEC specifications, these products are designed for a variety of memory modules such as RDIMM, LRDIMM, NVDIMM, UDIMM, SODIMM, MRDIMM, etc., to enable high-speed, large-capacity, high-reliability and low-power memory solutions for high-performance computing. Montage is quickly growing to become the leader in these industries, with revenue having grown 171% in the last 5 years!

About the Role

The Role:

We are seeking a Senior Software/Firmware Engineer to develop, debug, and optimize the DDR firmware for memory initialization, training, and margining that brings up and configures memory subsystems across our silicon platforms. This is a hands-on role focused on implementing training and margining algorithms, memory initialization sequences, and low-level firmware that enables reliable, high-performance memory operation from first power-on through production. You will collaborate with partner firmware teams, silicon design, memory subsystem architecture, and lab validation teams throughout the development lifecycle — from pre-silicon RTL simulation through post-silicon bring-up and characterization.

Responsibilities

• Key Responsibilities:
• Develop, debug, and maintain embedded firmware and low-level software for memory training, initialization, and margining (e.g., DDR5 PHY training, receive-enable, read DqDqs training, MBIST/RMT, eye/timing-voltage margining, DRAM controller initialization).
• Implement and optimize memory training and margining algorithms in collaboration with hardware designers and memory subsystem architects.
• Develop and run margining sweeps and eye-margin analysis to characterize and optimize DDR timing/voltage margins across process, voltage, and temperature (PVT).
• Work with signal integrity and equalization techniques — including CTLE, DFE, and related receiver equalization/training — to tune link margins and optimize high-speed DDR signal quality.
• Support memory initialization, configuration, training, and runtime management across the platform lifecycle.
• Debug hardware/firmware interactions during bring-up and post-silicon validation.
• Define and execute firmware-hardware co-validation plans together with the validation team.
• Develop scripts and tools to automate lab equipment, training sweeps, margin sweeps, and data analysis.
• Drive bench validation, characterization, and correlation of training and margining results against specifications.
• Create and maintain firmware design documentation, training/margining algorithm descriptions, and implementation notes.

Qualifications

• Required Skills & Experience
• Please do not apply unless you have a minimum of 5 years of relevant experience.
• B.S. or M.S. in Electrical Engineering, Computer Engineering, or Computer Science.
• 5-15 years of relevant experience in embedded firmware, low-level software, or memory subsystem (DDR/DDR5) development.

Required Skills

• Proven experience in embedded firmware or low-level software development, including bare-metal programming and low-level APIs on microcontrollers.
• Proficiency in C (and C++) for embedded/firmware development.
• Hands-on experience with memory subsystems — DDR/DDR5 JEDEC spec, DIMM configurations, and memory controller and/or DDR PHY firmware.
• Experience developing or implementing memory training algorithms, memory initialization sequences, and DDR margining (e.g., Rank Margin Tool/RMT, eye margining, timing/voltage margin sweeps).
• Experience with system/silicon bring-up and debugging complex platform issues.
• Familiarity with JTAG debuggers, source-level debuggers, and logging tools.
• Scripting proficiency in Python and Bash.
• Experience with lab bring-up/validation of high-speed memory IO — bench testing and characterization; DDRx characterization preferred.
• Proficiency with validation hardware, board design fundamentals, and high-speed lab equipment (oscilloscopes, BERTs, signal generators, logic/protocol analyzers).
• Strong analytical, debugging, and problem-solving skills.
• Effective verbal and written communication; ability to work cross-functionally with hardware, architecture, verification, and validation teams.
• Experience with Git or similar source control systems.

Preferred Skills

• Preferred / Desired Skills
• Familiarity with high-speed SerDes or memory interface Physical Layer (PHY) blocks.
• Experience with Design for Test (DFT) methodologies, MBIST, and memory test patterns.
• Experience with RTOS and other embedded OS environments.
• Microprocessor architecture — memory management units, interrupt delivery, and multithreaded development.
• Knowledge of memory-adjacent interfaces: SPI, eSPI, I2C, I3C, PCIe.
• Experience working on server platforms.
• Experience with ATE and/or system testing.
• Knowledge of signal integrity concepts and high-speed digital/PCB design.

Montage is an Equal Opportunity Employer. We do not discriminate based on race, color, religion, sex, national origin, age, disability, genetic information, veteran status, sexual orientation, or gender identity. We are committed to providing equal employment opportunities to all qualified applicants and employees