Senior Custom Memory Design Engineer (SRAM & IP Signoff)

NUVACORE; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

NUVACORE in Santa Clara is seeking a Custom Memory Design Engineer to drive end-to-end memory development—from schematic design to tape-out—while optimizing PPA across advanced CMOS nodes. You will own memory IP signoff and collaborate with foundry, CAD, RTL, and DFT teams to ensure robust performance.

The role demands hands-on transistor-level design, SPICE accuracy, and a track record of silicon-validated memory IP in high-volume products, with strong communication across teams.

Qualifications

• BS or MS in electrical engineering with 8+ years in custom memory design (SRAM/register files).
• Transistor-level circuit design experience with memory arrays (bit cells, sense amps, decoders) in advanced CMOS nodes.

Responsibilities

• Own schematic development and characterize custom memories to optimize PPA at advanced process nodes.
• Supervise layout implementation, macro floor planning, critical routing specifications, and PDV closure.
• Own end-to-end memory IP signoff: schematic and layout through DRC/LVS/antenna, parasitic extraction, and characterization across PVT corners.

Skills

Custom memory design

Schematic design

PDV closure

Memory signoff

SPICE simulations

Timing/power modeling

Education

BS or MS in Electrical Engineering

Tools

EDA tools

Extraction/Layout tools

Job description

NUVACORE in Santa Clara is seeking a Custom Memory Design Engineer to drive end-to-end memory development—from schematic design to tape-out—while optimizing PPA across advanced CMOS nodes. You will own memory IP signoff and collaborate with foundry, CAD, RTL, and DFT teams to ensure robust performance.

The role demands hands-on transistor-level design, SPICE accuracy, and a track record of silicon-validated memory IP in high-volume products, with strong communication across teams.