Senior CPU Custom Layout & Memory Design Lead

NUVACORE, Inc.; Santa Clara, Northern (CA, KY); Hybrid; USD 170,000 - 250,000; Full time

Job summary

Nuvacore, Inc. is seeking a CPU Custom Library and Memory Layout Lead to drive end-to-end layout of custom library cells and memory arrays for a high-performance CPU project.

You will own floorplanning, place-and-route, and DRC/LVS cleanup, while collaborating with circuit design, foundry, and CAD teams to optimize PPA and yield. Ideal candidates have 12+ years in advanced CMOS layout, strong knowledge of DRC/LVS, and hands-on experience with GAA nodes, automation, and vendor management.

Qualifications

• BS or MS in Electrical/Computer Engineering with 12+ years in custom/standard-cell and/or memory layout at advanced CMOS nodes.
• Transistor-level layout experience with static circuits and state-retaining elements (latches, flops) and memory arrays.
• Deep knowledge of DRC/LVS/antenna rules, parasitic extraction, and layout-versus-schematic closure using industry tools (Virtuoso, Calibre, StarRC).
• Understanding of layout-dependent effects, matching and symmetry, and impact on PPA and variation.
• Experience providing layout-driven feedback to foundries on PPA, yield, and DRC/PDK improvements.
• Strong communication and collaboration skills with circuit design, foundry, and CAD teams.
• Experience with Gate-All-Around (GAA) nodes is preferred.

Responsibilities

• Lead physical layout of custom library cells and memory arrays at advanced nodes.
• Own end-to-end layout closure: floorplanning, place-and-route, DRC/LVS/antenna cleanup, extraction hand-off, and LDE mitigation.
• Collaborate with circuit design, Foundry/PDK, CAD, and DFT teams to optimize layout for PPA, manufacturability, and yield; validate IP on testchips.
• Define and drive layout methodologies and automation—P-cell/script-based generation and DRC/LVS regression.
• Manage layout vendors/contractors: set scope, targets, and review deliverables for PPA, DRC/LVS, and methods compliance.

Skills

Custom layout

Memory layout

DRC/LVS

Parasitic extraction

Python/Tcl

GAA familiarity

Vendor management

Education

BS or MS in ECE/CS

Tools

Virtuoso

Calibre

StarRC

Job description

Nuvacore, Inc. is seeking a CPU Custom Library and Memory Layout Lead to drive end-to-end layout of custom library cells and memory arrays for a high-performance CPU project.

You will own floorplanning, place-and-route, and DRC/LVS cleanup, while collaborating with circuit design, foundry, and CAD teams to optimize PPA and yield. Ideal candidates have 12+ years in advanced CMOS layout, strong knowledge of DRC/LVS, and hands-on experience with GAA nodes, automation, and vendor management.