Senior NVM & Memory Circuit Designer

Future Ventures; Palo Alto (CA); On-site; USD 178,000 - 240,000; Full time

Job summary

Mythic in Palo Alto, CA, seeks a highly skilled engineer to design and verify NVM-based circuits for advanced product architecture. You will work on IP macros and full-chip interfaces, ensuring optimum performance and area while collaborating with validation and backend teams to accelerate silicon release.

The role requires hands-on circuit design, full-chip simulation, and verification with experience in NVM, Python, Verilog-A, and SystemVerilog. Strong communication and teamwork are essential.

Qualifications

• Ph.D. or MS in EE required; 3+ years industrial experience.
• Hands-on circuit design, full-chip simulation, debugging and verification.
• NVM embedded or NVM product experience is a plus.
• Modeling circuits using Python, Verilog-A, SystemVerilog Real Number Modeling is a plus.
• Experience with memory circuit blocks: decoder, HV switches, charge pumps, HV/LV regulators, bandgap, high-performance sense amps.
• Strong knowledge of semiconductor device physics and advanced process technology.
• Experience tapeout activities, layout supervision, silicon debugging, teamwork and communication.

Responsibilities

• Participate in design and verify IP macros for Mythic product architecture using available NVM technologies.
• Involve in NVM architecture for optimum performance and area.
• Design and verify new circuits to handshake with analog computation blocks.
• Design, optimize and verify NVM circuits including HV generator, x-path and y-path, test and peripheral circuits.
• Participate in RNM and functional modeling of NVM circuits for verification.
• Verify functional blocks and full chip interfacing with NVM design.
• Collaborate with validation engineers to expedite silicon evaluation; work with backend teams for production qualification.

Skills

Circuit design

Full-chip verification

NVM architecture

Python/Verilog-A/SystemVerilog

Memory block design

Communication skills

Self-starting

Education

Ph.D. or MS in EE

Tools

SPICE

Cadence

Verilog simulation

Job description

Mythic in Palo Alto, CA, seeks a highly skilled engineer to design and verify NVM-based circuits for advanced product architecture. You will work on IP macros and full-chip interfaces, ensuring optimum performance and area while collaborating with validation and backend teams to accelerate silicon release.

The role requires hands-on circuit design, full-chip simulation, and verification with experience in NVM, Python, Verilog-A, and SystemVerilog. Strong communication and teamwork are essential.