Senior CPU Physical Design Engineer: PPA & Signoff Pro

Socket.dev; Austin (TX); On-site; USD 163,000 - 236,000; Full time

Job summary

Google seeks a senior IC design specialist to join our hardware team in Austin, TX. You will collaborate with architecture, RTL, and DFT groups to optimize power, performance, and area while steering physical design from synthesis to Place-and-Route.

You will also tackle critical timing paths and lead signoff activities, including STA and electrical checks, to ensure robust, high-performance silicon. Compensation includes base salary with a target bonus and equity, reflecting market norms for

Qualifications

• Bachelor's degree or equivalent practical experience in EE/CSE/related field.
• 8 years of experience with high-speed digital design and PPA optimization.
• Experience with sign-off convergence domains including STA, electrical checks, or physical verification.

Responsibilities

• Partner with architecture, RTL, and DFT teams to optimize Power, Performance, and Area trade-offs.
• Own block and IP-level physical design implementation from synthesis through Place and Route.
• Debug critical timing paths and apply advanced physical design techniques to solve timing challenges.
• Execute signoff activities including Static Timing Analysis, power recovery, and electrical layout checks.

Skills

High-speed digital design

PPA optimization

Sign-off convergence domains

Static Timing Analysis (STA)

Electrical checks

Physical verification

AI/ML-assisted techniques

Data mining for QoR metrics

Python

Tcl

Perl

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Equivalent practical experience

Master's or PhD with emphasis on computer architecture

Tools

Python

Tcl

Perl

Job description

Google seeks a senior IC design specialist to join our hardware team in Austin, TX. You will collaborate with architecture, RTL, and DFT groups to optimize power, performance, and area while steering physical design from synthesis to Place-and-Route.

You will also tackle critical timing paths and lead signoff activities, including STA and electrical checks, to ensure robust, high-performance silicon. Compensation includes base salary with a target bonus and equity, reflecting market norms for