Senior CPU Physical Design Engineer - PPA and Timing Leader

Google; Mountain View (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

Google in Mountain View, CA is hiring a senior hardware design engineer to develop custom silicon and drive physical design excellence. You will own block- and IP-level implementation from synthesis through Place & Route, collaborate with architecture, RTL and DFT teams to optimize Power, Performance and Area, and address timing challenges with advanced techniques.

Individual pay is determined by experience; US: $163000 - $236000 (USD) with 15% bonus target plus equity and benefits.

Qualifications

• Eight years of experience in high‑speed digital design and PPA optimization.
• Experience with sign-off convergence domains such as STA and physical verification.
• Bachelor's degree or equivalent practical experience in a related field.

Responsibilities

• Collaborate with architecture, RTL, and DFT teams to optimize PPA trade-offs.
• Own block and IP‑level implementation from synthesis through Place and Route.
• Debug timing paths and apply advanced physical design techniques to meet timing.
• Execute signoff activities including STA, power recovery, and electrical checks.

Skills

High-speed digital design

STA/Physical verification

PPA optimization

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science

Tools

Python

Tcl

Perl

Job description

Google in Mountain View, CA is hiring a senior hardware design engineer to develop custom silicon and drive physical design excellence. You will own block- and IP-level implementation from synthesis through Place & Route, collaborate with architecture, RTL and DFT teams to optimize Power, Performance and Area, and address timing challenges with advanced techniques.

Individual pay is determined by experience; US: $163000 - $236000 (USD) with 15% bonus target plus equity and benefits.