Senior CPU Physical Design Engineer, Silicon

Google

Austin (TX)

On-site

USD 156,000 - 229,000

Full time

14 days+

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Benefits offered by this job

Bonus

Equity

Comprehensive benefits package

Job summary

A leading technology company in Austin, TX seeks a Senior CPU Physical Design Engineer to develop custom silicon solutions that enhance performance and efficiency. The ideal candidate has 5+ years of experience with physical design flow and a Bachelor's degree in a related field. This position offers a competitive salary ranging from $156,000 to $229,000, along with bonus and equity options.

Qualifications

5 years of experience with physical design flow and high-speed design.
Experience in one or more sign-off convergence areas.
Excellent knowledge of electromigration and voltage drop flows.

Responsibilities

Drive architectural feasibility studies and identify design tradeoffs.
Implement physical design methodologies using EDA tools.
Work on sign off areas such as Static Timing Analysis.

Skills

Physical design flow

Static Timing Analysis

Scripting

Data mining

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree or PhD in relevant field

Tools

Industry-standard EDA tools

Job description

Senior CPU Physical Design Engineer, Silicon

Base pay range

$156,000.00/yr - $229,000.00/yr

Minimum qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
5 years of experience with physical design flow such as constraints, synthesis, floor planning, place and route, clock tree synthesis (CTS), or physical verification.
Experience in one or more sign-off convergence areas.
Experience in high-speed design, including implementation and Power Performance Area, leveraging industry-standard tools.

Preferred qualifications

Master\'s degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
Experience in the delivery of high performance silicon in latest technology process nodes.
Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
Knowledge of Static Timing Analysis including sign-off corner definitions.
Knowledge of electromigration, voltage drop flows, and design for high frequency designs to support reliability.
Excellent scripting and data mining skills.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google\'s direct-to-consumer products. You\'ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google\'s mission is to organize the world\'s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people\'s lives better through technology.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

Work with Frontend and Architecture teams to drive architectural feasibility studies, and identify power-performance-area tradeoffs for physical design closure.
Drive block/IP physical design implementation and drive continuous power and performance improvements.
Develop physical design methodologies using industry standard EDA tools and developing design customization for implementation.
Work on sign off areas such as Static Timing Analysis and Electrical Checks.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google\'s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Seniority level