Senior CPU Physical Design Engineer – AI-Driven PPA & Equity

Google Inc.; Austin, Mountain View (TX, CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google Austin is hiring a Senior CPU Physical Design Engineer to drive block and IP-level implementation, from synthesis through Place and Route, collaborating with architecture, RTL, and DFT teams to optimize Power, Performance, and Area.

You will partner across Google’s silicon teams to push boundaries on high-speed digital design, sign-off convergence, and timing closure, delivering world-class hardware for consumer products while mentors and champions best practices in physical design.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 8 years of experience with high-speed digital design, implementation, and Power, Performance, and Area (PPA) optimization.
• Experience with sign-off convergence domains, including Static Timing Analysis (STA), electrical checks, or physical verification.

Responsibilities

• Partner with architecture, RTL, and DFT teams to optimize Power, Performance, and Area trade-offs.
• Own block and IP-level physical design implementation from synthesis through Place and Route.
• Debug critical timing paths and apply advanced physical design techniques to solve timing challenges.
• Execute signoff activities, including Static Timing Analysis, power recovery, and electrical layout checks.

Skills

High-speed digital design

STA/physical verification

PPA optimization

Sign-off convergence

Python scripting

Tcl scripting

Perl scripting

Education

Bachelor's degree in Electrical/Computer Engineering or CS

Master's degree in Electrical/Computer Engineering or CS

PhD in Electrical/Computer Engineering or CS

Job description

Google Austin is hiring a Senior CPU Physical Design Engineer to drive block and IP-level implementation, from synthesis through Place and Route, collaborating with architecture, RTL, and DFT teams to optimize Power, Performance, and Area.

You will partner across Google’s silicon teams to push boundaries on high-speed digital design, sign-off convergence, and timing closure, delivering world-class hardware for consumer products while mentors and champions best practices in physical design.