Senior CPU Physical Design Engineer

Socket.dev; Austin (TX); On-site; USD 163,000 - 236,000; Full time

Job summary

Google seeks a senior IC design specialist to join our hardware team in Austin, TX. You will collaborate with architecture, RTL, and DFT groups to optimize power, performance, and area while steering physical design from synthesis to Place-and-Route.

You will also tackle critical timing paths and lead signoff activities, including STA and electrical checks, to ensure robust, high-performance silicon. Compensation includes base salary with a target bonus and equity, reflecting market norms for

Qualifications

• Bachelor's degree or equivalent practical experience in EE/CSE/related field.
• 8 years of experience with high-speed digital design and PPA optimization.
• Experience with sign-off convergence domains including STA, electrical checks, or physical verification.

Responsibilities

• Partner with architecture, RTL, and DFT teams to optimize Power, Performance, and Area trade-offs.
• Own block and IP-level physical design implementation from synthesis through Place and Route.
• Debug critical timing paths and apply advanced physical design techniques to solve timing challenges.
• Execute signoff activities including Static Timing Analysis, power recovery, and electrical layout checks.

Skills

High-speed digital design

PPA optimization

Sign-off convergence domains

Static Timing Analysis (STA)

Electrical checks

Physical verification

AI/ML-assisted techniques

Data mining for QoR metrics

Python

Tcl

Perl

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Equivalent practical experience

Master's or PhD with emphasis on computer architecture

Tools

Python

Tcl

Perl

Job description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 8 years of experience with high-speed digital design, implementation, and Power, Performance, and Area (PPA) optimization.
• Experience with sign-off convergence domains, including Static Timing Analysis (STA), electrical checks, or physical verification.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with advanced process nodes (e.g., 5nm, 3nm, 2nm, or below).
• Experience applying AI/ML-assisted techniques for physical design closure and PPA scaling.
• Proficiency in scripting (Python, Tcl, Perl) and data mining for QoR metrics.
• Understanding of EMIR flows, power grid design, and design reliability for high-frequency circuits.

About the job:

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities:

• Partner with architecture, RTL, and DFT teams to optimize Power, Performance, and Area trade-offs.
• Own block and IP-level physical design implementation from synthesis through Place and Route.
• Debug critical timing paths and apply advanced physical design techniques to solve timing challenges.
• Execute signoff activities, including Static Timing Analysis, power recovery, and electrical layout checks.