Senior CPU Physical Design Engineer

Google; Portland (OR); On-site; USD 163,000 - 236,000; Full time

Job summary

Google is seeking a seasoned hardware designer in Portland to advance custom silicon; collaborate with architecture, RTL, and DFT teams to optimize power, performance, and area from synthesis through Place and Route in a high-speed environment.

You will tackle sign-off convergence, STA, and verification steps, applying advanced physical design techniques and contributing to products used worldwide. Competitive package includes base salary, 15% bonus target, equity, and benefits.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with high-speed digital design, implementation, and Power, Performance, and Area (PPA) optimization.
• Experience with sign-off convergence domains, including Static Timing Analysis (STA), electrical checks, or physical verification.

Responsibilities

• Partner with architecture, RTL, and DFT teams to optimize Power, Performance, and Area trade-offs.
• Own block and IP-level physical design implementation from synthesis through Place and Route.
• Debug critical timing paths and apply advanced physical design techniques to solve timing challenges.
• Execute signoff activities, including Static Timing Analysis, power recovery, and electrical layout checks.

Skills

High-speed digital design

PPA optimization

Static Timing Analysis (STA)

Electrical checks

Physical verification

Sign-off convergence domains

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science

Tools

Python

Tcl

Perl

Job description

In most instances, this position requires in-person interviews as part of the hiring process.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Austin, TX, USA; Mountain View, CA, USA; Portland, OR, USA; Poughkeepsie, NY, USA.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with high-speed digital design, implementation, and Power, Performance, and Area (PPA) optimization.
• Experience with sign-off convergence domains, including Static Timing Analysis (STA), electrical checks, or physical verification.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with advanced process nodes (e.g., 5nm, 3nm, 2nm, or below).
• Experience applying AI/ML-assisted techniques for physical design closure and PPA scaling.
• Proficiency in scripting (Python, Tcl, Perl) and data mining for QoR metrics.
• Understanding of EMIR flows, power grid design, and design reliability for high-frequency circuits.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Responsibilities

Learn more about benefits at Google.

• Partner with architecture, RTL, and DFT teams to optimize Power, Performance, and Area trade-offs.
• Own block and IP-level physical design implementation from synthesis through Place and Route.
• Debug critical timing paths and apply advanced physical design techniques to solve timing challenges.
• Execute signoff activities, including Static Timing Analysis, power recovery, and electrical layout checks.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.