CPU Physical Design Engineer - Full Time

RosaicLabs Inc; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Medical (including HSA)

Dental

Vision

Life & AD&D

401(k)

Job summary

RosaicLabs Inc in Santa Clara, CA is seeking a senior IC design engineer to lead CPU block design and physical implementation. You will analyze microarchitectures, own gate-level design, and drive CTS, P&R, and signoff across complex blocks. Collaboration with RTL, verification, and packaging teams is essential.

The role emphasizes heavy involvement in timing, power, and area closure, plus debug of DRC/LVS across corners. A strong background in high-speed ASIC design and SPS flows is required.

Qualifications

• Master's degree or higher in Electrical/Computer Engineering or related field.
• Hands-on experience in CPU/high-performance ASIC physical design.
• Strong understanding of pipelines, caches, branch prediction, and interconnects.

Responsibilities

• Analyze CPU microarchitecture to guide timing/power/area tradeoffs.
• Develop and own gate-level design for CPU blocks and clock-domain/reset architecture.
• Perform transistor-level design for critical paths and memory structures.
• Drive synthesis, floorplanning, CTS, placement, routing to closure.
• Own STA, signal integrity, IR drop, electromigration, and signoff.
• Debug and close timing, power, and DRC/LVS violations across corners.
• Collaborate with RTL, DFT, verification, and package teams to optimize PPA.
• Develop and improve physical design flows, scripts, and methodologies.

Skills

CPU microarchitecture understanding

Gate-level design experience

Scripting in Tcl/Perl/Python

PPA tradeoffs and debugging

Analytical thinking

Education

Master's degree in Electrical or Computer Engineering

Tools

EDA tools for synthesis/PR/signoff

Job description

• Analyze CPU microarchitecture (pipeline stages, execution units, cache hierarchy, branch prediction) to guide implementation tradeoffs on timing, power, and area
• Develop and own gate-level design for CPU blocks: standard-cell selection, logic restructuring, and clock-domain/reset architecture
• Perform transistor-level design and custom circuit work for critical-path structures (register files, custom datapaths, memory arrays, high-speed logic)
• Drive logic synthesis, floorplanning, power planning, placement, clock-tree synthesis (CTS), and routing to closure
• Own static timing analysis (STA), signal integrity, IR drop/electromigration analysis, and physical/electrical signoff
• Debug and close timing, power, and DRC/LVS violations across corners and modes
• Collaborate with RTL design, DFT, verification, and package/system teams to co-optimize PPA (power, performance, area)
• Develop and improve physical design flows, scripts, and methodologies to boost QoR and turnaround time
• Participate in design reviews, correlate silicon results with pre-silicon predictions, and drive root-cause debug of PPA gaps

What you'll do

• Analyze CPU microarchitecture (pipeline stages, execution units, cache hierarchy, branch prediction) to guide implementation tradeoffs on timing, power, and area
• Develop and own gate-level design for CPU blocks: standard-cell selection, logic restructuring, and clock-domain/reset architecture
• Perform transistor-level design and custom circuit work for critical-path structures (register files, custom datapaths, memory arrays, high-speed logic)
• Drive logic synthesis, floorplanning, power planning, placement, clock-tree synthesis (CTS), and routing to closure
• Own static timing analysis (STA), signal integrity, IR drop/electromigration analysis, and physical/electrical signoff
• Debug and close timing, power, and DRC/LVS violations across corners and modes
• Collaborate with RTL design, DFT, verification, and package/system teams to co-optimize PPA (power, performance, area)
• Develop and improve physical design flows, scripts, and methodologies to boost QoR and turnaround time
• Participate in design reviews, correlate silicon results with pre-silicon predictions, and drive root-cause debug of PPA gaps

What we're looking for

• Master's degree in Electrical Engineering, Computer Engineering, or a related field
• 5+ years of industry experience in CPU or high-performance ASIC physical design
• Strong understanding of CPU microarchitecture: pipelines, out-of-order execution, caches, branch prediction, and interconnect
• Hands-on experience with gate-level design, including standard-cell logic design and clock/reset architecture
• Working knowledge of transistor-level/custom circuit design for high-speed and low-power structures
• Proven track record driving synthesis and place-and-route (P&R) to timing, power, and area closure on complex blocks
• Solid grasp of static timing analysis (STA), signal integrity, and physical verification (DRC/LVS)
• Proficiency with industry-standard EDA tools for synthesis, P&R, and signoff (see Tools & Technologies)
• Scripting proficiency in Tcl, Perl, or Python for flow automation
• Strong analytical and debugging skills, with the ability to work through cross-corner, cross-mode PPA tradeoffs

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

Benefits: Medical (including HSA plans), Dental, Vision, Employee Life & AD&D, 401(k)