CPU Physical Design Engineer — Core Blocks & SoC

Intel Corporation; Hillsboro (OR); Hybrid; USD 122,000 - 232,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel Corporation in Hillsboro, Oregon is seeking a mid-level Physical Design Engineer for CPU cores. You will contribute to RTL-to-GDS flows, performing synthesis, floorplanning, PnR, and design closure while collaborating with RTL, verification, and full-chip teams.

The role emphasizes ownership, ongoing learning, and cross-functional collaboration in a fast-paced semiconductor environment with opportunities to impact high-performance silicon across client and server platforms.

Qualifications

• Bachelor's or Master's degree in a relevant engineering field with multiple years of IC design experience.
• Experience with logic synthesis, place and route, STA and design closure.
• PV convergence, DRC/LVS, noise and electromigration checks, and formal equivalence.
• Scripting in TCL plus at least one other language (e.g., Python, Perl).
• Exposure to CPU digital logic synthesis within large SoC or IP context.

Responsibilities

• Execute physical design implementation for CPU core blocks or subsystems.
• Perform synthesis, floor planning, place and route, and design closure activities.
• Conduct STA, power analysis, and physical verification.
• Identify and debug timing, power, and design rule violations.
• Develop scripts for design automation and collaborate with RTL, verification, clocking, and full-chip teams.

Skills

Scripting (TCL)

Python scripting

IC design experience

Education

Bachelor's degree in Computer or Electrical Engineering

Master's degree in same field

Tools

Synopsys/Cadence toolchain

PrimeTime

ICC2

Genus/Innovus

Fusion Compiler

Job description

Intel Corporation in Hillsboro, Oregon is seeking a mid-level Physical Design Engineer for CPU cores. You will contribute to RTL-to-GDS flows, performing synthesis, floorplanning, PnR, and design closure while collaborating with RTL, verification, and full-chip teams.

The role emphasizes ownership, ongoing learning, and cross-functional collaboration in a fast-paced semiconductor environment with opportunities to impact high-performance silicon across client and server platforms.