Senior CPU RTL & Microarchitecture Engineer

Intel Corporation; Austin (TX); Híbrido; USD 142.000 - 269.000; Jornada completa

Descripción de la vacante

Intel Corporation in Austin, TX seeks a CPU Logic Design Engineer to drive RTL development and verification for next-generation CPUs. You will shape architecture features, optimize power, performance, and area, and ensure design integrity through RTL and MAS documentation.

Collaboration with SoC customers will ensure high-quality integration. Minimum 5+ years in CPU RTL using SystemVerilog and 3+ years scripting are required, with strong problem solving and cross-team collaboration skills.

Formación

• Bachelor's degree in electrical engineering, computer engineering, or computer science with 5+ years of relevant experience.
• 5+ years experience in CPU RTL design using SystemVerilog, with strong knowledge of logic design, simulation, and debug.
• 3+ years experience in scripting languages such as TCL, Perl, or Python.

Responsabilidades

• Develop and optimize logic design, RTL coding, and simulation for the CPU.
• Participate in defining the architecture and microarchitecture features of the CPU design.
• Write RTL and optimize logic for power, performance, area, and timing goals.
• Ensure design integrity for physical implementation through effective strategies, tools, and methods.
• Review verification plans to ensure design features are correctly validated and resolve failing RTL tests.
• Document microarchitectural specifications (MAS) for the CPU features.
• Collaborate with SoC customers to ensure seamless integration and high-quality performance of the CPU block.

Conocimientos

SystemVerilog

RTL design

Power-aware design

Cross-clock domain crossings

Scripting (Python/TCL/Perl)

Debugging & verification

Static timing analysis / UPF

Educación

Bachelor's degree in electrical engineering, computer engineering, or computer science

Master's degree in same field

Herramientas

UPF

lint checks

Descripción del empleo

Intel Corporation in Austin, TX seeks a CPU Logic Design Engineer to drive RTL development and verification for next-generation CPUs. You will shape architecture features, optimize power, performance, and area, and ensure design integrity through RTL and MAS documentation.

Collaboration with SoC customers will ensure high-quality integration. Minimum 5+ years in CPU RTL using SystemVerilog and 3+ years scripting are required, with strong problem solving and cross-team collaboration skills.