Senior CPU Physical Design Engineer - High-Performance SoC

Socket.dev; Austin (TX); On-site; USD 138,000 - 197,000; Full time

Job summary

Socket.dev in Austin, Texas is seeking a senior hardware design engineer to execute block-level physical design from synthesis through Place-and-Route and signoff. You will collaborate with RTL, architecture, and DFT teams to meet tight timing, power, and area goals while delivering scalable, high-performance silicon.

Applicants should have 4+ years in digital physical design, strong scripting in Python or Tcl, and hands-on experience with STA and PnR tools.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 4 years of experience with digital physical design implementation, including synthesis, Place and Route (PnR), and timing closure.
• Experience in high-performance, low-power physical design implementation or design convergence with industry standard synthesis, PnR and signoff tools.

Responsibilities

• Execute block-level physical design implementation from synthesis, Place and Route and design convergence via signoff checks.
• Analyze and resolve timing, congestion, and power issues to achieve optimal Power, Performance, and Area.
• Collaborate with cross-functional teams including RTL, Architecture, and DFT to align design constraints.
• Perform signoff activities, including Static Timing Analysis, physical verification, and power checks.

Skills

Digital PnR & timing

Low-power design experience

Design convergence with industry tools

Education

Bachelor's degree in EE/CE/CS or related

Master's degree or PhD in EE/CE/CS

Tools

STA tooling

Physical verification tools

Python/Tcl scripting

Job description

Socket.dev in Austin, Texas is seeking a senior hardware design engineer to execute block-level physical design from synthesis through Place-and-Route and signoff. You will collaborate with RTL, architecture, and DFT teams to meet tight timing, power, and area goals while delivering scalable, high-performance silicon.

Applicants should have 4+ years in digital physical design, strong scripting in Python or Tcl, and hands-on experience with STA and PnR tools.