Senior Physical Design Engineer – High-Performance CPU, 3nm

MediaTek

Austin (TX)

On-site

USD 128,600 - 217,200

Full time

14 days+
Application generator

Get a reply from this employer — a resume and cover letter tailored to exactly what they’re hiring for.

Get past ATS filters

Benefits offered by this job

Health insurance
Life and disability insurance
401(k) plan
Paid holidays
Paid time off

Job summary

MediaTek in Austin, TX is seeking a senior physical design engineer to lead APR for 3nm and other nodes, develop clock-tree optimization, and collaborate across front‑end, STA, IR/EM, and verification teams. You will apply 5+ years of CPU physical design experience, with strong scripting in Perl, Python, TCL and Make, and a deep knowledge of floorplanning, placement, CTS, routing, and signoff.

Salary range reflects US market norms; benefits include health and life insurance, 401(k), paid

Qualifications

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field (or equivalent experience).
  • Minimum of 5 years of hands-on experience in physical design implementation (APR) for complex SoCs or IP.
  • Strong scripting skills in Perl, Python, TCL, and Make for flow automation and productivity improvement.
  • Solid understanding of physical design concepts, including floorplanning, placement, CTS, routing, and signoff.
  • Experience with CPU physical implementation is a strong plus.
  • Additional experience with synthesis, formal equivalence checking, flow automation, IR analysis, and STA analysis is highly desirable.
  • Effective communication and teamwork skills in a cross-functional, global environment.

Responsibilities

  • Perform APR implementation and PV signoff for high-performance CPU designs in 3nm and other advanced nodes.
  • Develop and optimize clock tree structures to meet performance, power, and skew/jitter targets.
  • Conduct early-stage PPA evaluation and risk assessment to guide architectural decisions.
  • Collaborate with front-end design, STA, IR/EM, and verification teams to close timing, power, and physical design issues.
  • Support and enhance design methodologies and flows to improve quality, scalability, and turnaround time.

Skills

APR implementation
Physical design
Scripting: Perl
Scripting: Python
Scripting: TCL
Scripting: Make
Cross-functional collaboration
Communication

Education

Bachelor’s or Master’s in Electrical/Computer Engineering

Tools

Synthesis tools
Formal equivalence checking
Flow automation tools
STA analysis

Job description

MediaTek in Austin, TX is seeking a senior physical design engineer to lead APR for 3nm and other nodes, develop clock-tree optimization, and collaborate across front‑end, STA, IR/EM, and verification teams. You will apply 5+ years of CPU physical design experience, with strong scripting in Perl, Python, TCL and Make, and a deep knowledge of floorplanning, placement, CTS, routing, and signoff.

Salary range reflects US market norms; benefits include health and life insurance, 401(k), paid

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Senior Physical Design Engineer — 3nm CPU APR & Signoff
Senior Physical Design Engineer — 3nm CPU APR & Signoff

MediaTek Research Lab Inc. • Austin (TX)

On-site
USD 128,600 - 217,200
Health insurance
401(k) plan
Paid time off
+1
Senior Physical Design Engineer
Senior Physical Design Engineer

MediaTek Research Lab Inc. • Austin (TX)

On-site
USD 128,600 - 217,200
Health insurance
401(k) plan
Paid time off
+1
Senior Physical Design Engineer
Senior Physical Design Engineer

MediaTek • Austin (TX)

On-site
USD 128,600 - 217,200
Health insurance
Life and disability insurance
401(k) plan
+2
Senior CPU Physical Design Engineer
Senior CPU Physical Design Engineer

Intel Corporation • Austin (TX), Northern (KY)

Hybrid
USD 106,000 - 200,000
Senior Physical Design Engineer – Hybrid ASIC/SoC P&R
Senior Physical Design Engineer – Hybrid ASIC/SoC P&R

TSMC - Taiwan Semiconductor Manufacturing Company Limited • Austin (TX)

Hybrid
USD 107,000 - 162,000
Physical Design Methodology Lead Engineer
Physical Design Methodology Lead Engineer

AMD • Austin (TX)

On-site
USD 170,000 - 210,000
Senior Physical Design Lead — RTL to GDSII, 4nm/3nm
Senior Physical Design Lead — RTL to GDSII, 4nm/3nm

MediaTek Research Lab Inc. • San Jose (CA)

On-site
USD 179,000 - 286,000
Comprehensive health insurance
401(k) plan
Paid holidays and sick leave
+1
Senior Physical Design Engineer - High-Speed ASICs (5nm/3nm)
Senior Physical Design Engineer - High-Speed ASICs (5nm/3nm)

Lumilens • San Jose (CA)

On-site
USD 180,000 - 240,000
Health insurance
Professional development
Cutting-edge technology access
+2
Senior CPU Physical Design & Integration Engineer
Senior CPU Physical Design & Integration Engineer

Apple Inc. • California (MO)

On-site
USD 150,000 - 278,000
Senior RTL Design Manager for High-Performance SoCs
Senior RTL Design Manager for High-Performance SoCs

MediaTek Research Lab Inc. • Austin (TX), Northern (KY)

Hybrid
USD 175,000 - 229,000
Health insurance
Savings plan
Paid holidays
+3