CPU Physical Design Engineer — High-Performance Silicon

Google; Austin (TX); On-site; USD 138,000 - 197,000; Full time

Job summary

Google is hiring for a senior block-level physical design engineer to develop custom silicon powering its products. You will work on high-performance, low-power architectures, collaborating with RTL, architecture, and DFT teams to meet tight parity and timing goals.

The role emphasizes signoff discipline, STA, physical verification, and QoR improvements to deliver efficientcompute blocks, with input on preferred working location from Austin, TX or Mountain View, CA.

Qualifications

• Bachelor’s degree or equivalent practical experience in EE/CS.
• 4 years of experience with digital physical design, synthesis, Place and Route (PnR), and timing closure.
• Experience in high-performance, low-power physical design implementation with industry standard tools.

Responsibilities

• Execute block-level physical design implementation from synthesis, Place and Route and design convergence via signoff checks.
• Analyze and resolve timing, congestion, and power issues to achieve optimal Power, Performance, and Area.
• Collaborate with cross-functional teams including RTL, Architecture, and DFT to align design constraints.
• Perform signoff activities, including Static Timing Analysis, physical verification, and power checks.

Skills

Digital physical design

Synthesis

Place and Route (PnR)

Timing closure

Low-power design

Education

Bachelor's degree in EE/CE/CS or related field

Master's degree or PhD with emphasis on computer architecture

Tools

STA tools

Physical verification tools

Electrical checks tooling

Python scripting

Tcl scripting

Job description

Google is hiring for a senior block-level physical design engineer to develop custom silicon powering its products. You will work on high-performance, low-power architectures, collaborating with RTL, architecture, and DFT teams to meet tight parity and timing goals.

The role emphasizes signoff discipline, STA, physical verification, and QoR improvements to deliver efficientcompute blocks, with input on preferred working location from Austin, TX or Mountain View, CA.