Senior CPU Core Physical Design Engineer - High-Performance

Jobtailor; California (MO); On-site; USD 150,000 - 190,000; Full time

Job summary

Jobtailor is seeking a senior hardware design engineer to drive physical design for customized CPUs. You will translate RTL to GDS, manage synthesis, place & route, and timing analysis while ensuring signoff and formal verification.

The role emphasizes power, frequency, and area optimization and close collaboration with EDA vendors. Ideal candidates bring 4–6+ years of VLSI experience, strong timing analysis, and low-power design skills, with familiarity in x86 architectures and scripting in

Qualifications

• Bachelor's degree in a STEM field required; advanced degree preferred.
• 6+ years of experience or a Master's with 4+ years of experience.
• 4+ years in VLSI circuit design and synthesis.
• 4+ years in static timing analysis.
• 4+ years in low power design.
• 2+ years in x86 CPU architecture preferred.
• Proficiency in Tcl/Perl/Python programming preferred.

Responsibilities

• Perform physical design implementation of custom CPU designs from RTL to GDS.
• Conduct all aspects of physical design flow including synthesis, place and route, timing analysis.
• Conduct verification and signoff including formal equivalence verification.
• Optimize CPU design to improve power, frequency, and area.
• Collaborate with EDA vendors to enhance tool capabilities.

Skills

VLSI circuit design

Synthesis

Place & Route

Static timing analysis

Low power design

x86 CPU architecture

Scripting (Python/Tcl/Perl)

Education

Bachelor's degree in Electrical/Electronic Engineering or Computer Engineering

Master's degree in a related STEM field (preferred)

Tools

Synthesis tools

Place & Route tools

Static Timing Analysis tools

Job description

Jobtailor is seeking a senior hardware design engineer to drive physical design for customized CPUs. You will translate RTL to GDS, manage synthesis, place & route, and timing analysis while ensuring signoff and formal verification.

The role emphasizes power, frequency, and area optimization and close collaboration with EDA vendors. Ideal candidates bring 4–6+ years of VLSI experience, strong timing analysis, and low-power design skills, with familiarity in x86 architectures and scripting in