Physical Design Architect/Technical Manager

Highbrow Technology Inc; San Francisco (CA); On-site; USD 180,000 - 300,000; Full time

Job summary

Highbrow Technology Inc in San Francisco, CA seeks an experienced Physical Design Architect / Technical Manager to drive RTL-to-GDSII implementation for cutting-edge ASIC/SoC at advanced nodes. You will own physical implementation from synthesis to tape-out, focusing on PPA and timing closure.

The role requires hands-on flow optimization, floorplanning, CTS, routing, and collaboration with RTL and power teams across global sites; expected to develop automation in Tcl/Python and evaluate new EDA

Qualifications

• 15+ years of ASIC/SoC physical design and timing closure experience.
• Strong RTL-to-GDSII implementation and successful tape-outs at 5nm or below.
• Hands-on experience with DC/Genus, Innovus/ICC2, PrimeTime, RedHawk/Voltus, and Calibre.
• Expertise in SoC floorplanning, power distribution, CTS, routing, and timing convergence for high-frequency designs.
• Experience with large SoCs (>100M gates) operating above 1GHz.
• Strong scripting skills in Tcl, Python, Perl, or Shell.
• Excellent collaboration across cross-functional and global engineering teams.

Responsibilities

• Own the physical implementation of complex ASIC/SoC designs from logic synthesis through GDSII.
• Perform floorplanning, place and route, clock tree synthesis, timing closure, IR drop, electromigration, and physical verification.
• Drive physical-aware design decisions to optimize power, performance, and area (PPA).
• Partner with RTL engineers to improve partitioning, resolve congestion and timing issues, and implement ECOs.
• Develop automation using Tcl, Python, Perl, or Shell to improve implementation efficiency and quality.
• Evaluate new EDA tools and collaborate with vendors to enhance physical design flows.
• Deliver high-quality physical implementation for advanced process technologies (5nm and below).

Skills

ASIC/SoC design

Timing closure

Scripting (Tcl, Python, Perl, Shell)

Tools

DC/Genus

Innovus/ICC2

PrimeTime

RedHawk/Voltus

Calibre

Job description

We are looking for an experienced Physical Design Architect / Technical Manager to drive the implementation of complex, low-power, high-performance ASIC and SoC designs at advanced technology nodes. If you're passionate about RTL-to-GDSII implementation, timing closure, and delivering world-class silicon, we'd love to connect.

In this role, you will:

• Own the physical implementation of complex ASIC/SoC designs from logic synthesis through GDSII.
• Perform floorplanning, place and route, clock tree synthesis, timing closure, IR drop, electromigration, and physical verification.
• Drive physical-aware design decisions to optimize power, performance, and area (PPA).
• Partner with RTL engineers to improve partitioning, resolve congestion and timing issues, and implement ECOs.
• Develop automation using Tcl, Python, Perl, or Shell to improve implementation efficiency and quality.
• Evaluate new EDA tools and collaborate with vendors to enhance physical design flows.
• Deliver high-quality physical implementation for advanced process technologies (5nm and below).

Qualifications

• 15+ years of ASIC/SoC physical design and timing closure experience.
• Strong understanding of RTL-to-GDSII implementation and successful tape-outs at 5nm or below.
• Hands-on experience with DC/Genus, Innovus/ICC2, PrimeTime, RedHawk/Voltus, and Calibre.
• Expertise in SoC floorplanning, power distribution, CTS, routing, and timing convergence for high-frequency designs.
• Experience with large SoCs (>100M gates) operating above 1GHz.
• Strong scripting skills in Tcl, Python, Perl, or Shell.
• Excellent collaboration skills across cross-functional and global engineering teams.