Senior CPU Cache & Subsystem Design Lead

Google; Portland (OR); On-site; USD 240,000 - 333,000; Full time

Job summary

Google is seeking a senior CPU design leader to drive front-end design for next-generation CPU subsystems. You will guide a team of engineers through microarchitecture, RTL, and integration into target SOCs, balancing performance, power, and area.

You will lead cross-functional collaboration with architecture, software, verification, power, and physical design, defining schedules and delivering high-quality RTL on time.

Qualifications

• Master's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 15 years of experience in high-performance CPU design, including load-store unit logic/RTL and L2/L3 private/shared caches including microarchitecture definition and PPA optimizations.
• Experience leading technical teams for modern processor subsystems with high speed, lower power design.
• Experience with front-end quality checks (e.g., Lint, CDC/RDC).

Responsibilities

• Lead a team of digital design engineers working on CPU subsystems with a focus on microarchitecture and RTL design for next-generation CPUs.
• Review and propose performance-enhancing microarchitecture features in collaboration with cross-functional teams.
• Deliver comprehensive plans to meet project milestones and ensure production-quality designs.
• Collaborate with verification, physical design, and power analysis teams to meet frequency, power, and area targets.
• Direct load-store unit and cache subsystem design optimizations to improve performance and efficiency.

Skills

CPU design

RTL

microarchitecture

front-end checks

Education

Master's degree in EE/CS

Tools

ARM ISA

Mobile SOC

Job description

Google is seeking a senior CPU design leader to drive front-end design for next-generation CPU subsystems. You will guide a team of engineers through microarchitecture, RTL, and integration into target SOCs, balancing performance, power, and area.

You will lead cross-functional collaboration with architecture, software, verification, power, and physical design, defining schedules and delivering high-quality RTL on time.