Staff CPU RTL Engineer - Microarchitecture & SoC

Google; Mountain View (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google is hiring in Mountain View, CA for a senior RTL design engineer focused on CPU subsystems and AI accelerators. You will define microarchitecture, implement front-end RTL, and optimize for performance, power, and area while collaborating with Software, Architect, and Verification teams.

We value experience with SystemVerilog, UPF/Lint, and a strong grasp of PPA trade‑offs. Individual pay includes bonus and equity, with a broad benefits package.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 8 years of experience in CPU or AI accelerator logic/RTL design, including microarchitecture definition and PPA optimizations.
• Experience with RTL language (System Verilog) and related design processes (e.g., Lint, UPF).

Responsibilities

• Participate in developing CPU subsystem. Develop CPU subsystem front-end designs, emphasizing microarchitecture and RTL design for the next generation CPU.
• Propose performance enhancing microarchitecture features, and work with Software, Architect, and Performance teams for trade‑off studies.
• Communicate the pros and cons of microarchitecture enhancements. Deliver designs, meeting PPA goals with production quality.
• Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals.
• Become familiar with modern techniques, interpret the techniques into design constructs, and languages to provide guidance to and participate in the performance evaluation effort.

Skills

RTL design

SystemVerilog

PPA optimization

microarchitecture

communication

Education

Bachelor's degree or equivalent

Master's or PhD preferred

Tools

Lint

UPF

ARM ISA

SOC design

Job description

Google is hiring in Mountain View, CA for a senior RTL design engineer focused on CPU subsystems and AI accelerators. You will define microarchitecture, implement front-end RTL, and optimize for performance, power, and area while collaborating with Software, Architect, and Verification teams.

We value experience with SystemVerilog, UPF/Lint, and a strong grasp of PPA trade‑offs. Individual pay includes bonus and equity, with a broad benefits package.