Lead CPU Cache Subsystem Design Engineer - Senior Staff

Google LLC; Austin, Mountain View (TX, CA); Hybride; USD 240 000 - 333 000; Plein temps

Résumé du poste

Google is seeking a Senior Staff CPU Cache Subsystem Design Engineer to lead front-end design teams, define microarchitecture, and deliver RTL for next-generation CPU subsystems across target SOCs. You will collaborate with architecture, software, verification, power, DFT, and physical design teams to optimize performance, power, and area.

Ideal candidates have a Master’s in EE/CS, 15 years in high-performance CPU design, and experience guiding technical teams, with familiarity in Lint, CDC/RDC

Qualifications

• Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 15 years of experience in high-performance CPU design, including load-store unit logic/RTL and L2/L3 private/shared caches including microarchitecture definition and PPA optimizations.
• Experience leading technical teams for modern processor subsystems with high speed, lower power design.
• Experience with front-end quality checks (e.g., Lint, CDC/RDC).

Responsabilités

• Lead a front-end design team for CPU subsystems across target SOCs.
• Collaborate with architecture, software, verification, power, DFT, and physical design teams to define microarchitecture and deliver high quality RTL.
• Evaluate design options considering complexity, performance, power, and area with schedule in mind.
• Work with cross-functional teams to meet project goals and milestones.
• Deliver designs that balance performance, power, and area while satisfying timelines.

Connaissances

CPU microarchitecture design

RTL design (load-store unit, caches)

Front-end design leadership

Frontend verification, power, DFT

Formation

Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience

Outils

ARM instruction set architecture

Mobile SOC architecture

Performance/power optimization tools

Description du poste

Google is seeking a Senior Staff CPU Cache Subsystem Design Engineer to lead front-end design teams, define microarchitecture, and deliver RTL for next-generation CPU subsystems across target SOCs. You will collaborate with architecture, software, verification, power, DFT, and physical design teams to optimize performance, power, and area.

Ideal candidates have a Master’s in EE/CS, 15 years in high-performance CPU design, and experience guiding technical teams, with familiarity in Lint, CDC/RDC