Senior Staff CPU Cache Subsystem Design Engineer

Google; Portland (OR); Sur place; USD 240 000 - 333 000; Plein temps

Résumé du poste

Google is seeking a senior CPU design leader to drive front-end design for next-generation CPU subsystems. You will guide a team of engineers through microarchitecture, RTL, and integration into target SOCs, balancing performance, power, and area.

You will lead cross-functional collaboration with architecture, software, verification, power, and physical design, defining schedules and delivering high-quality RTL on time.

Qualifications

• Master's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 15 years of experience in high-performance CPU design, including load-store unit logic/RTL and L2/L3 private/shared caches including microarchitecture definition and PPA optimizations.
• Experience leading technical teams for modern processor subsystems with high speed, lower power design.
• Experience with front-end quality checks (e.g., Lint, CDC/RDC).

Responsabilités

• Lead a team of digital design engineers working on CPU subsystems with a focus on microarchitecture and RTL design for next-generation CPUs.
• Review and propose performance-enhancing microarchitecture features in collaboration with cross-functional teams.
• Deliver comprehensive plans to meet project milestones and ensure production-quality designs.
• Collaborate with verification, physical design, and power analysis teams to meet frequency, power, and area targets.
• Direct load-store unit and cache subsystem design optimizations to improve performance and efficiency.

Connaissances

CPU design

RTL

microarchitecture

front-end checks

Formation

Master's degree in EE/CS

Outils

ARM ISA

Mobile SOC

Description du poste

In most instances, this position requires in-person interviews as part of the hiring process.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Austin, TX, USA; Mountain View, CA, USA; Portland, OR, USA; Poughkeepsie, NY, USA.

Minimum qualifications

• Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 15 years of experience in high-performance CPU design, including load-store unit logic/RTL and L2/L3 private/shared caches including microarchitecture definition and PPA optimizations.
• Experience leading technical teams for modern processor subsystems with high speed, lower power design.
• Experience with front-end quality checks (e.g., Lint, CDC/RDC).

Preferred qualifications

• Experience with ARM instruction set architecture.
• Experience with mobile CPU subsystem.
• Experience with mobile SOC architecture/integration.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will contribute to all phases of complex designs of CPU subsystems from design specification to productization, including integration into target SOCs.

You will lead a front-end design team, collaborate with members of architecture, software, verification, power, DFT, physical design teams to define the microarchitecture and schedule in delivering high quality RTL that meets project goals.

You’ll help your team grow and solve technical problems with innovative micro-architecture and practical logic solutions. You will be responsible for evaluating and deciding on the best design options with complexity, performance, power and area and schedule in mind.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $240000 - $333000 (USD) + 25% bonus target + equity + benefits

Responsibilities

Learn more about benefits at Google.

• Lead a team of digital design engineers working on CPU functional units, focusing specifically on microarchitecture and RTL design for next-generation CPU subsystems.
• Review and propose performance-enhancing microarchitecture features while collaborating closely with cross-functional software, architecture, and performance teams on trade-off studies.
• Deliver comprehensive plans to achieve project milestones and execution goals, ensuring the production-quality design meets strict scheduling targets.
• Collaborate directly with verification, physical design, and power analysis teams to ensure designs successfully meet frequency, power, and area targets.
• Direct load-store unit and cache subsystem design optimizations across CPU components to deliver power, performance, and area metrics.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.