Senior Staff CPU Cache Subsystem Design Engineer

Google LLC; Austin, Mountain View (TX, CA); Hybrid; USD 240,000 - 333,000; Full time

Job summary

Google is seeking a Senior Staff CPU Cache Subsystem Design Engineer to lead front-end design teams, define microarchitecture, and deliver RTL for next-generation CPU subsystems across target SOCs. You will collaborate with architecture, software, verification, power, DFT, and physical design teams to optimize performance, power, and area.

Ideal candidates have a Master’s in EE/CS, 15 years in high-performance CPU design, and experience guiding technical teams, with familiarity in Lint, CDC/RDC

Qualifications

• Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 15 years of experience in high-performance CPU design, including load-store unit logic/RTL and L2/L3 private/shared caches including microarchitecture definition and PPA optimizations.
• Experience leading technical teams for modern processor subsystems with high speed, lower power design.
• Experience with front-end quality checks (e.g., Lint, CDC/RDC).

Responsibilities

• Lead a front-end design team for CPU subsystems across target SOCs.
• Collaborate with architecture, software, verification, power, DFT, and physical design teams to define microarchitecture and deliver high quality RTL.
• Evaluate design options considering complexity, performance, power, and area with schedule in mind.
• Work with cross-functional teams to meet project goals and milestones.
• Deliver designs that balance performance, power, and area while satisfying timelines.

Skills

CPU microarchitecture design

RTL design (load-store unit, caches)

Front-end design leadership

Frontend verification, power, DFT

Education

Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience

Tools

ARM instruction set architecture

Mobile SOC architecture

Performance/power optimization tools

Job description

Senior Staff CPU Cache Subsystem Design Engineer

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X In most instances, this position requires in-person interviews as part of the hiring process.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Austin, TX, USA; Mountain View, CA, USA; Portland, OR, USA; Poughkeepsie, NY, USA.

• Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 15 years of experience in high-performance CPU design, including load-store unit logic/RTL and L2/L3 private/shared caches including microarchitecture definition and PPA optimizations.
• Experience leading technical teams for modern processor subsystems with high speed, lower power design.
• Experience with front-end quality checks (e.g., Lint, CDC/RDC).

Preferred qualifications:

• Experience with ARM instruction set architecture.
• Experience with mobile CPU subsystem.
• Experience with mobile SOC architecture/integration.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will contribute to all phases of complex designs of CPU subsystems from design specification to productization, including integration into target SOCs.

You will lead a front-end design team, collaborate with members of architecture, software, verification, power, DFT, physical design teams to define the microarchitecture and schedule in delivering high quality RTL that meets project goals.

You'll help your team grow and solve technical problems with innovative micro-architecture and practical logic solutions. You will be responsible for evaluating and deciding on the best design options with complexity, performance, power and area and schedule in mind.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will contribute to all phases of complex designs of CPU subsystems from design specification to productization, including integration into target SOCs.

You will lead a front-end design team, collaborate with members of architecture, software, verification, power, DFT, physical design teams to define the microarchitecture and schedule in delivering high quality RTL that meets project goals.

You'll help your team grow and solve technical problems with innovative micro-architecture and practical logic solutions. You will be responsible for evaluating and deciding on the best design options with complexity, performance, power and area and schedule in mind.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $240000 - $333000 (USD) + 25% bonus target + equity + benefits

Learn more about benefits at Google .

• Lead a team of digital design engineers working on CPU functional units, focusing specifically on microarchitecture and RTL design for next-generation CPU subsystems.
• Review and propose performance-enhancing microarchitecture features while collaborating closely with cross-functional software, architecture, and performance teams on trade-off studies.
• Deliver comprehensive plans to achieve project milestones and execution goals, ensuring the production-quality design meets strict scheduling targets.
• Collaborate directly with verification, physical design, and power analysis teams to ensure designs successfully meet frequency, power, and area targets.
• Direct load-store unit and cache subsystem design optimizations across CPU components to deliver power, performance, and area metrics.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.