Senior CPU Physical Design Engineer - PPA & AI/ML Flows

Google; Mountain View (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google in Mountain View is seeking a seasoned hardware design leader to own end-to-end physical design for top-level CPU blocks. You will drive PPA optimization, pioneering design methodologies and AI/ML-enhanced flows, while addressing complex timing, power, and verification challenges.

The role requires extensive experience in high-performance, low-power design and cross-functional collaboration with Architecture, RTL, DFT, and Tech partners.

Qualifications

• Bachelor’s degree or equivalent practical experience in EE/CE/CS.
• 10 years of experience in physical design, PPA optimization, and signoff convergence.
• Experience with high-performance, low-power physical design and standard/custom tool flows.

Responsibilities

• Lead end-to-end physical design strategy and execution for top-level CPU blocks.
• Pioneer novel physical design methodologies, tool flows, and AI/ML optimization to maximize PPA.
• Resolve complex timing, power grid, EMIR, and physical verification bottlenecks.
• Drive technical roadmaps, mentor senior engineers, and influence architectural trade-offs.

Skills

Physical design

PPA optimization

Signoff convergence

Low-power design

Synthesis/PnR/Signoff tools

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Synthesis tools

P&R tools

Signoff tools

Job description

Google in Mountain View is seeking a seasoned hardware design leader to own end-to-end physical design for top-level CPU blocks. You will drive PPA optimization, pioneering design methodologies and AI/ML-enhanced flows, while addressing complex timing, power, and verification challenges.

The role requires extensive experience in high-performance, low-power design and cross-functional collaboration with Architecture, RTL, DFT, and Tech partners.