Senior CPU RTL Engineer, Silicon Microarchitecture

Google; Portland (OR); On-site; USD 192,000 - 278,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

Google is seeking a senior hardware engineer to shape the next generation of custom silicon. You will lead CPU subsystem front-end designs, drive microarchitecture decisions, and align RTL with PPA targets, collaborating with Software, Architect, and Performance teams to optimize trade‑offs.

The role emphasizes front-end design leadership for modern processor components or AI accelerators, with opportunities to influence ARM ISA integration and SOC design.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field.
• 8 years of experience in CPU or AI accelerator logic/RTL design with microarchitecture and PPA focus.
• Experience with RTL language SystemVerilog and related design processes (Lint, UPF).

Responsibilities

• Develop CPU subsystem front-end designs with focus on microarchitecture and RTL.
• Propose performance-enhancing features and work with software and performance teams on trade-offs.
• Communicate architecture pros/cons and deliver production-quality designs meeting PPA goals.
• Collaborate with Verification, physical design and power teams to meet frequency, power, and area targets.
• Translate modern techniques into design constructs and guide performance evaluation efforts.

Skills

CPU/AI accelerator design

RTL design

SystemVerilog

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Tools

UPF

Job description

Google is seeking a senior hardware engineer to shape the next generation of custom silicon. You will lead CPU subsystem front-end designs, drive microarchitecture decisions, and align RTL with PPA targets, collaborating with Software, Architect, and Performance teams to optimize trade‑offs.

The role emphasizes front-end design leadership for modern processor components or AI accelerators, with opportunities to influence ARM ISA integration and SOC design.