Senior CPU RTL Engineer - Microarchitecture & Frontend

Google; Mountain View (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google is hiring a hardware engineer to contribute to the CPU frontend designs, focusing on microarchitecture and RTL for the next generation CPU. You will collaborate with architects to propose energy-efficient features and trade-offs while ensuring designs meet PPA goals.

Ideal candidates bring 8+ years of RTL and digital logic experience, Verilog/SystemVerilog expertise, and a strong background in logic synthesis for performance and low power.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering, Computer Science or related field, or equivalent practical experience.
• 8 years of experience with digital logic design principles, RTL design concepts and Verilog/SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.

Responsibilities

• Contribute to CPU frontend designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
• Propose performance enhancing microarchitecture features with efficiency in mind and work with architects and performance teams for trade-off studies.
• Communicate pros and cons of microarchitecture enhancements and facilitate final decision making.
• Deliver designs meeting Power, Performance and Area goals with production quality.
• Become familiar with techniques for at least one processor functional block and translate techniques into design constructs.

Skills

RTL design

Verilog/SystemVerilog

Digital logic

Synthesis techniques

Low-power design

Education

Bachelor's degree in EE/CS or related

8 years of relevant experience

Job description

Google is hiring a hardware engineer to contribute to the CPU frontend designs, focusing on microarchitecture and RTL for the next generation CPU. You will collaborate with architects to propose energy-efficient features and trade-offs while ensuring designs meet PPA goals.

Ideal candidates bring 8+ years of RTL and digital logic experience, Verilog/SystemVerilog expertise, and a strong background in logic synthesis for performance and low power.