Senior ASIC Verification Lead for AI Inference

Tensordyne; United States; Remote; USD 180,000 - 320,000; Full time

Benefits offered by this job

Flexible spending

Bonusly awards

Meals & snacks

Job summary

Tensordyne, a Sunnyvale/remote-friendly AI accelerator startup, seeks a senior ASIC verification lead to drive pre-silicon correctness for next-generation AI inference processors. You will own verification strategy, tests, and sign-off, collaborating with design and architecture teams to meet ambitious goals.

Ideal candidates bring 15+ years in ASIC verification, SystemVerilog/UVM expertise, and a passion for innovative AI hardware.

Qualifications

• 15+ years ASIC verification experience
• Expert in SystemVerilog, UVM, Constraint Randomization, Functional Coverage
• Experience in C/C++ or System-C
• Deep understanding of object oriented programming, constrained random stimulus, and coverage driven verification
• Verification experience of high-speed interfaces (PCIe, Ethernet, DDR/HBM, SerDes)
• Scripting experience (Python, Perl, TCL, shell programming)
• Interest to explore AI architectures for convolution, transformer and other workloads
• Self-starter and highly-motivated to work in a dynamic start-up environment
• B.S. (M.S. preferred) degree in Electrical or Computer engineering (or similar field)

Responsibilities

• Ensure the pre-silicon correctness and quality of a multi-million gate ASIC that integrates computational accelerators and 3rd-party SoC IP blocks
• SoC/Subsystem verification of embedded CPUs such as ARM/RISC-V and interconnect subsystem (including C and assembly diag validation)
• Lead verification planning from architecture through tapeout
• Develop block-level, sub-system and full-chip verification environment and tests to implement test plans
• Establish reusable verification methodologies and frameworks - scale testbenches to subsystem and full chip environments
• Work closely with design and architecture teams to understand the functional and performance goals of the design; and work together to make the design-under-test work under all specified circumstances
• Triage and debug functional and performance issues with the design-under-test
• Drive verification signoff criteria and quality metrics - handle bug tracking, coverage convergence, regression failures
• Mentor and technically guide verification engineers helping them through test planning and verification closure
• Perform diagnostic and post-silicon validation tests in the lab

Skills

SystemVerilog

UVM

Constraint Randomization

Functional Coverage

C/C++

SystemC

PCIe

Ethernet

DDR/HBM

SerDes

Python

Perl

TCL

Shell

AI workloads

Education

B.S. in Electrical or Computer Engineering

Tools

ARM CPU

RISC-V

Python

Perl

Job description

Tensordyne, a Sunnyvale/remote-friendly AI accelerator startup, seeks a senior ASIC verification lead to drive pre-silicon correctness for next-generation AI inference processors. You will own verification strategy, tests, and sign-off, collaborating with design and architecture teams to meet ambitious goals.

Ideal candidates bring 15+ years in ASIC verification, SystemVerilog/UVM expertise, and a passion for innovative AI hardware.