Senior ASIC Architect for AI Inference Hardware

Tensordyne; United States; Remote; USD 200,000 - 320,000; Full time

Job summary

Tensordyne is seeking an experienced ASIC Architect to lead the architectural planning and design of its next‑generation AI processors for inference acceleration. You will drive high‑level silicon architectures, mentor teams, prototype design concepts, and ensure performance, power, and manufacturability targets are met.

Ideal candidates bring 15+ years in silicon design for HPC, strong Verilog‑based RTL, and experience mapping advanced AI workloads to hardware, with an MS/PhD in EE or related

Qualifications

• 15+ years of hands‑on silicon design and architectural planning for HPC processors.
• Strong understanding of generative AI hardware mappings and high‑throughput SIMD workloads.
• Proficiency in Verilog, RTL verification, and performance modeling.

Responsibilities

• Lead architectural planning and definition of new Tensordyne AI processors with specialized cores and interconnects.
• Develop design specifications, model architectures, and milestones for ASIC development.
• Mentor cross‑functional teams and guide design reviews with external partners and internal stakeholders.
• Evaluate silicon IP, EDA tools, and methodologies to improve design efficiency.

Skills

Silicon design

Architectural planning

HPC processors

C/C++

Education

MS or PhD in Electrical Engineering or related field

Tools

Verilog

SystemC

Job description

Tensordyne is seeking an experienced ASIC Architect to lead the architectural planning and design of its next‑generation AI processors for inference acceleration. You will drive high‑level silicon architectures, mentor teams, prototype design concepts, and ensure performance, power, and manufacturability targets are met.

Ideal candidates bring 15+ years in silicon design for HPC, strong Verilog‑based RTL, and experience mapping advanced AI workloads to hardware, with an MS/PhD in EE or related