Senior ASIC Design Engineer — AI Inference Architect Remote

Tensordyne; United States; Remote; USD 180,000 - 260,000; Full time

Benefits offered by this job

Medical insurance

Vision insurance

Dental insurance

Meals and snacks

Drinks

Unlimited PTO

Job summary

Tensordyne is seeking a Sr. ASIC designer to lead micro-architecture and RTL implementation for high-performance AI accelerators. You will integrate CPU IP into SoC, coordinate with front-end and physical teams, and drive timing, power, and verification tasks in a dynamic startup setting.

The role requires 10+ years of ASIC RTL experience, strong Verilog/SystemVerilog skills, and familiarity with ARM/RISC-V/MIPS architectures, AMBA protocols, and powerful debugging capabilities.

Qualifications

• 10+ years of ASIC design experience with RTL logic design in multi-million gate ASICs using Verilog or SystemVerilog.
• Experience in CPU IP integration into SoC.
• Knowledge of ARM/RISC-V/MIPS architectures, memory hierarchy, cache coherency, virtual memory, multicore CPU operation.

Responsibilities

• Author micro-architecture specifications and participate in reviews.
• Architect and implement complex RTL designs.
• Scope third party IP requirements and solicit vendors.
• Integrate CPU and other relevant IPs into the CPU sub-system.
• Collaborate with the physical design team to resolve timing and power issues.
• Analyze code coverage and provide feedback to verification.
• Perform diagnostic and post-silicon validation tests and assist software bring-up.

Skills

RTL design

Verilog/SystemVerilog

CPU IP into SoC

ARM/RISC-V/MIPS

AMBA/AXI/APB

Peripheral interfaces SPI/eMMC/GPIO/I2

Power/UPF

Timing closure

AI architectures interest

Education

Bachelor's in Electrical or Computer Engineering

MS preferred

Job description

Tensordyne is seeking a Sr. ASIC designer to lead micro-architecture and RTL implementation for high-performance AI accelerators. You will integrate CPU IP into SoC, coordinate with front-end and physical teams, and drive timing, power, and verification tasks in a dynamic startup setting.

The role requires 10+ years of ASIC RTL experience, strong Verilog/SystemVerilog skills, and familiarity with ARM/RISC-V/MIPS architectures, AMBA protocols, and powerful debugging capabilities.