Senior ASIC Verification Engineer — Remote & Flexible Hours

Tensordyne; United States; Remote; USD 140,000 - 210,000; Full time

Benefits offered by this job

Medical, Vision, Dental

Meals, snacks, drinks

Flexible work hours

Generous PTO

Job summary

Tensordyne in the United States is seeking a senior ASIC verification engineer to lead pre-silicon validation for our next-generation AI inference processors. You will drive test plans, develop UVM-based environments, and collaborate with design teams to meet performance goals.

The role requires SystemVerilog expertise, experience with PCIe/Ethernet/DDR, and scripting in Python or TCL. You will mentor junior engineers and help scale verification for multi-million gate chips in a fast-paced

Qualifications

• 4-8 years of ASIC verification experience, leading chips through verification and post-silicon validation.
• Expertise in SystemVerilog, UVM, constraint randomization, and functional coverage.
• Experience in C/C++ or System-C.
• Strong OO programming principles and coverage-driven verification approach.
• Verification of high-speed interfaces (PCIe, Ethernet, DDR/HBM, SerDes).
• Scripting experience (Python, Perl, TCL, shell).
• Interest in AI architectures for convolution, transformer workloads.

Responsibilities

• Lead verification planning from architecture through tapeout.
• Develop block-, subsystem-, and full-chip verification environments and tests.
• Scale testbenches to subsystems and full-chip contexts.
• Triage and debug functional and performance issues in the DUT.
• Mentor verification engineers and guide test planning and closure.
• Run diagnostic and post-silicon validation tests in the lab.

Skills

SystemVerilog

UVM

Constraint Randomization

Functional Coverage

C/C++ or SystemC

PCIe

Ethernet

DDR/HBM

Scripting (Python, Perl, TCL)

Education

B.S. in Electrical or Computer Engineering

M.S. in Electrical or Computer Engineering

Job description

Tensordyne in the United States is seeking a senior ASIC verification engineer to lead pre-silicon validation for our next-generation AI inference processors. You will drive test plans, develop UVM-based environments, and collaborate with design teams to meet performance goals.

The role requires SystemVerilog expertise, experience with PCIe/Ethernet/DDR, and scripting in Python or TCL. You will mentor junior engineers and help scale verification for multi-million gate chips in a fast-paced