Senior ASIC Verification Architect — Remote & Flexible Hours

Tensordyne; Sunnyvale (CA); On-site; USD 150,000 - 200,000; Full time

Benefits offered by this job

Medical benefits

Flexible work hours

Generous PTO policy

Meals and snacks provided

Job summary

Tensordyne in Sunnyvale, California is seeking a senior ASIC verification engineer to lead the verification of next-generation processors aimed at generative AI inference acceleration. The role demands extensive experience in ASIC verification, particularly with System Verilog and UVM, aligning with dynamic market needs.

The ideal candidate will ensure pre-silicon correctness, mentor verification engineers, and contribute to a collaborative and innovative team culture. Join us in shaping groundbreaking AI technology.

Qualifications

• 15+ years of ASIC verification experience.
• Expert in System Verilog and UVM.
• Experience with high-speed interfaces.

Responsibilities

• Ensure pre-silicon correctness of multi-million gate ASIC.
• Lead verification planning from architecture through tapeout.
• Mentor verification engineers and guide test planning.

Skills

ASIC verification experience

System Verilog

UVM

C/C++ or System-C

Object-oriented programming

High-speed interfaces (PCIe, Ethernet)

Python scripting

Education

B.S. in Electrical or Computer Engineering

M.S. preferred

Job description

Tensordyne in Sunnyvale, California is seeking a senior ASIC verification engineer to lead the verification of next-generation processors aimed at generative AI inference acceleration. The role demands extensive experience in ASIC verification, particularly with System Verilog and UVM, aligning with dynamic market needs.

The ideal candidate will ensure pre-silicon correctness, mentor verification engineers, and contribute to a collaborative and innovative team culture. Join us in shaping groundbreaking AI technology.