Senior ASIC Verification Architect — DDR/Memory IP

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Comprehensive benefits package

Job summary

Synopsys, Inc. is seeking an experienced ASIC verification engineer in Sunnyvale to define verification plans, build constrained-random UVM testbenches, and write assertions to close coverage gaps.

You will debug complex memory interface issues and mentor junior engineers, shaping verification strategies for future product generations. The role requires 8+ years in ASIC verification, deep UVM/SystemVerilog expertise, and knowledge of DDR memory architectures, with scripting in Perl or Python to

Qualifications

• Bachelor’s degree in electrical engineering or computer engineering with 8+ years of hands-on ASIC verification experience.
• Deep proficiency in UVM methodology and SystemVerilog, you have built test benches that found bugs.
• Understanding of DDR memory architecture and DDR PHY design, including timing, training, and calibration flows.
• Knowledge of DFI protocol, memory controllers, or memory subsystem integration, preferred.
• Solid scripting ability in Perl or Python for automation, result parsing, and flow development.
• Proven debugging skills across RTL and gate-level simulations.
• Experience with AI-assisted verification tools and workflows is a plus.

Responsibilities

• Define and track verification test plans for DDR PHY and memory subsystem IP blocks, translating architecture specs into executable verification strategies.
• Design and write constrained-random SystemVerilog testbenches using UVM, building reusable verification components that scale across product families.
• Write SystemVerilog assertions and functional coverage models to close coverage gaps and catch protocol violations.
• Debug RTL and gate-level simulation failures, working with design engineers to root-cause issues in complex memory interface logic.
• Perform code coverage analysis and drive coverage closure, identifying untested paths and corner cases that matter.
• Mentor verification engineers earlier in their careers, reviewing test benches, debugging strategies, and verification plans.
• Integrate AI-assisted verification tools and workflows into the team's methodology.

Skills

ASIC verification

Debugging

Mentoring

Automation

Education

Bachelor’s degree in electrical engineering or computer engineering

Tools

UVM

SystemVerilog

Perl

Python

Job description

Synopsys, Inc. is seeking an experienced ASIC verification engineer in Sunnyvale to define verification plans, build constrained-random UVM testbenches, and write assertions to close coverage gaps.

You will debug complex memory interface issues and mentor junior engineers, shaping verification strategies for future product generations. The role requires 8+ years in ASIC verification, deep UVM/SystemVerilog expertise, and knowledge of DDR memory architectures, with scripting in Perl or Python to