Technologist, ASIC Verification Engineering

WarmStart Ltd; Milpitas (CA); Hybrid; USD 140,000 - 190,000; Full time

Job summary

Sandisk in Milpitas, CA is seeking a Senior IP Verification Engineer to strengthen the design verification team, focusing on functional correctness and performance of complex digital IP blocks.

You will develop verification plans and UVM-based testbenches, create UVCs, implement constrained-random stimulus, debug RTL issues, and drive coverage and regression, while mentoring junior engineers.

Qualifications

• BS/MS in Electrical/Computer Engineering or related field.
• 10+ years of IP verification experience.

Responsibilities

• Develop verification plans and testbenches using UVM.
• Create reusable verification components (UVCs) including agents, monitors, drivers, and scoreboards.
• Design constrained-random stimulus and coverage-driven verification strategies.
• Debug RTL issues and perform root cause analysis with design teams.
• Develop and maintain regression test suites and coverage metrics.
• Mentor junior engineers on UVM best practices.
• Review and improve verification infrastructure and coding standards.
• Contribute to IP-level and SoC-level verification.

Skills

SystemVerilog

UVM

Verification IP

Simulation tools

PCIe

DDR

AXI/AMBA

Python scripting

Debugging

Education

BS in Electrical Engineering

MS in Electrical Engineering

Tools

Cadence

Synopsys

Mentor

Job description

Sandisk is a leader in data solutions, known for its innovative Flash and memory technologies that power the digital world. With a commitment to sustainability and advanced manufacturing, Sandisk is recognized globally for its performance and quality. The company is seeking a Senior IP Verification Engineer to enhance its design verification team, focusing on ensuring the functional correctness and performance compliance of complex digital IP blocks.

Responsibilities:

• Develop comprehensive verification plans and testbenches using UVM methodology.
• Create reusable verification components (UVCs) including agents, monitors, drivers, and scoreboards.
• Design constrained-random stimulus and coverage-driven verification strategies.
• Debug RTL issues, perform root cause analysis, and collaborate with design teams.
• Develop and maintain regression test suites and coverage metrics.
• Mentor junior engineers on UVM best practices and verification methodologies.
• Review and improve verification infrastructure and coding standards.
• Contribute to IP-level and SoC-level integration verification.

Qualifications:

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in IP verification.

Skills:

• Expert-level proficiency in SystemVerilog and UVM methodology.
• Strong understanding of verification methodologies (constrained-random, coverage-driven, assertion-based).
• Hands-on experience developing reusable UVM testbenches and verification IP.
• Proficiency with simulation tools (Cadence, Synopsys, Mentor).
• Experience with industry-standard protocols (PCIe, DDR) and AMBA protocols (AXI, AHB, APB).
• Strong debugging skills using waveform viewers and simulation tools.
• Experience with coverage analysis and closure (functional, code, assertion).
• Knowledge of scripting languages (Python, Perl, Tcl, shell).
• Familiarity with formal verification and low-power verification is preferred.
• Understanding of SoC-level verification flows is preferred.
• Interest in AI/ML tools for coding and automation is a plus.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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