Senior ASIC Verification Engineer: UVM & SystemVerilog Expert

Sandisk; Illinois; On-site; USD 120,000 - 150,000; Full time

Job summary

Sandisk in Illinois is seeking an experienced ASIC Verification Engineer to define and document RTL development and verify complex strategic IPs. The role requires collaboration with architecture and SOC teams, focusing on significant contributions to design and methodology.

The ideal candidate should possess a BSc in Electrical Engineering and at least 10 years of industry experience in ASIC Verification. Strong analytical and communication skills are essential, along with a commitment to diversity and inclusion.

Qualifications

• Minimum 10 years of experience in ASIC Verification.
• Excellent analytical and debugging skills.
• Strong professional leading skills.

Responsibilities

• Define and document RTL development in Verilog/System Verilog.
• Work closely with architecture teams and SOC teams.
• Contribute to design and verification methodology.

Skills

ASIC Verification with UVM Methodology

System Verilog

Analytical and debugging skills

Advanced verbal and written communication skills

Leadership skills

Education

BSc in Electrical Engineering

Job description

Sandisk in Illinois is seeking an experienced ASIC Verification Engineer to define and document RTL development and verify complex strategic IPs. The role requires collaboration with architecture and SOC teams, focusing on significant contributions to design and methodology.

The ideal candidate should possess a BSc in Electrical Engineering and at least 10 years of industry experience in ASIC Verification. Strong analytical and communication skills are essential, along with a commitment to diversity and inclusion.