Senior ASIC Verification Engineer — Lead Coverage & UVM

People Consultancy Services (PCS); Sunnyvale (CA); Hybrid; USD 150,000 - 210,000; Full time

Job summary

People Consultancy Services (PCS) is seeking a highly motivated ASIC Verification Engineer to join our networking silicon development team in a hybrid Sunnyvale setting. You will own block-level verification, craft test plans, and drive coverage closure for complex SoCs.

You will build and refine advanced UVM environments, perform constrained random testing, and debug using industry tools. Collaboration with cross-functional teams is essential to deliver robust ASIC/SoC designs.

Qualifications

• 5+ years of ASIC/SoC verification experience with ownership from test plan to coverage closure.
• Strong expertise in SystemVerilog and UVM methodology, including building environments from scratch.
• Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
• Hands-on test planning, coverage analysis, and debugging of complex SoC designs.

Responsibilities

• Own and drive block-level or subsystem verification, from test plan to coverage closure.
• Develop, enhance, and maintain advanced UVM verification environments (agents, sequences, scoreboards, etc.).
• Perform constraint-driven random testing and debug complex SoC designs to meet coverage goals.
• Analyze simulation results using Cadence Xcelium, Synopsys VCS, and Mentor Questa, debugging waveforms to validate functionality.
• Collaborate with cross-functional teams to resolve issues and ensure high-quality ASIC/SoC deliverables.

Skills

SystemVerilog

UVM

Test planning

Coverage analysis

Assertions (SVA)

Debugging complex SoCs

Constraint-driven random testing

Tools

Cadence Xcelium

Synopsys VCS

Mentor Questa

Job description

People Consultancy Services (PCS) is seeking a highly motivated ASIC Verification Engineer to join our networking silicon development team in a hybrid Sunnyvale setting. You will own block-level verification, craft test plans, and drive coverage closure for complex SoCs.

You will build and refine advanced UVM environments, perform constrained random testing, and debug using industry tools. Collaboration with cross-functional teams is essential to deliver robust ASIC/SoC designs.