ASIC Verification Engineer (TERADYNE, North Reading, MA)

Teradyne; North Reading (MA); On-site; USD 123,000 - 197,000; Full time

Job summary

Teradyne in North Reading, MA seeks an ASIC Verification Engineer to join the Reference Model team. You will verify complex ASIC/SoC designs using SystemC, SystemVerilog/UVM, and constrained-random methods, collaborating with design, firmware, and software groups.

The role emphasizes verification planning, testbench architecture, and delivering high-quality results with rigorous methodologies. Bachelor’s degree required; Master’s preferred, with 4+ years in semiconductor verification.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field.
• 4+ years of ASIC/SoC verification experience in semiconductor product development.
• Experience with SystemC and C++.
• Object Oriented Programming experience.
• Experience developing verification environments using SystemVerilog and UVM.
• Deep understanding of functional verification methodologies, constrained-random verification, and coverage closure.

Responsibilities

• Verification planning, testbench architecture, and execution for complex ASIC and SoC designs.
• Develop and maintain SystemC and SystemVerilog/UVM reference models.
• Develop and maintain SystemVerilog/UVM-based verification environments, test cases, and reusable verification components.
• Collaborate closely with design, architecture, firmware, software, and validation teams to ensure comprehensive feature coverage.
• Build and execute verification strategies utilizing simulation, coverage-driven verification, assertions, and formal methodologies.
• Support debug and root-cause analysis of functional issues identified during verification and silicon bring-up activities.
• Partner with cross-functional teams to define verification requirements, milestones, and quality metrics.
• Ensure verification deliverables are completed with high quality, on schedule, and aligned with project objectives.

Skills

SystemC

C++

SystemVerilog/UVM

Python/Perl scripting

Functional verification

Constrained-random verification

Formal verification

Debugging complex designs

Silicon bring-up support

Education

Bachelor's degree in Electrical/Computer Engineering/CS

Master's degree preferred

Tools

EDA simulation tools

Job description

Select how often (in days) to receive an alert:

Date: Sep 15, 2026

Location: North Reading, MA, US

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Our Purpose

TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supportedto innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.

Opportunity Overview

As an ASIC Verification Engineer based in North Reading, MA, you will play a key role in the development and verification of complex ASIC and SoC designs that support Teradyne’s industry-leading products. You will join the ASIC Reference Model team, so this requires strong technical expertise in digital design verification methodologies, collaboration across engineering disciplines, and the ability to contribute to strategic verification initiatives while driving quality and execution excellence. This senior role aligns with professionals who work on complex issues requiring conceptual thinking, implement solutions for broadly defined problems, and contribute to the success of larger cross-functional projects.

• Verification planning, testbench architecture, and execution for complex ASIC and SoC designs.
• Develop and maintain SystemC and SystemVerilog/UVM reference models.
• Develop and maintain SystemVerilog/UVM-based verification environments, test cases, and reusable verification components.
• Collaborate closely with design, architecture, firmware, software, and validation teams to ensure comprehensive feature coverage.
• Build and execute verification strategies utilizing simulation, coverage-driven verification, assertions, and formal methodologies.
• Support debug and root-cause analysis of functional issues identified during verification and silicon bring-up activities.
• Partner with cross-functional teams to define verification requirements, milestones, and quality metrics.
• Ensure verification deliverables are completed with high quality, on schedule, and aligned with project objectives.

All About You

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position.

Required Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field; Master's degree preferred.
• 4+ years of ASIC/SoC verification experience in semiconductor product development.
• Experience with SystemC and C++.
• Object Oriented Programming experience.
• Experience developing verification environments using SystemVerilog and UVM.
• Deep understanding of functional verification methodologies, constrained-random verification, and coverage closure.
• Experience with assertion-based verification and scripting using Python, Perl, or similar languages.
• Knowledge of industry-standard EDA simulation and debug tools.
• Experience verifying complex digital designs, interconnects, memory subsystems, and high-speed interfaces.
• Strong analytical and problem-solving skills with the ability to debug complex functional issues.
• Excellent collaboration and communication skills in a cross-functional engineering environment.
• Preferred experience with formal verification methodologies.
• Preferred experience supporting silicon bring-up and post-silicon validation activities.

Compensation

The base salary range for this role is $123,100.00 to $196,900.00. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan

This job is eligible for discretionary bonus(es) based on financial performance.

Benefits

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details.

Job Segment

Testing, Electrical Engineering, Manufacturing Engineer, Test Engineer, Computer Science, Technology, Engineering