Senior ASIC Verification Engineer - Flexible Office Model

Jobs Paloaltonetworks; Santa Clara (CA); On-site; USD 129,000 - 209,000; Full time

Job summary

Palo Alto Networks is seeking a Design Verification engineer for the ASIC team in Santa Clara. You will define verification methodologies, architect test benches, write test plans, specify coverage, write tests, and debug across simulation, emulation, formal verification, and silicon validation.

Office-based with four days in the office per week, one day remote as needed. The role requires 5+ years in ASIC verification, strong SystemVerilog/UVM, and a track record from concept to mass

Qualifications

• BS in EE, CE, or CS or equivalent experience; MSEE preferred.
• 5+ years in ASIC design verification with pre-silicon focus.
• Proven track record shipping multiple ASIC products to mass production.
• Strong SystemVerilog/UVM expertise and test-plan development.
• Ability to design robust, scalable verification environments.

Responsibilities

• Define verification methodologies and architecture test benches.
• Develop test plans, coverage metrics, and constrained-random tests.
• Create and debug tests across simulation, emulation, and formal verification.
• Automate verification tasks with Python, and integrate scoreboards.
• Collaborate with ASIC teams to ensure features meet requirements.

Skills

SystemVerilog

UVM

Python

C/C++

Test benches

Coverage models

Education

BS in EE/CE/CS

Tools

Simulation

Emulation

Formal verification

Job description

Palo Alto Networks is seeking a Design Verification engineer for the ASIC team in Santa Clara. You will define verification methodologies, architect test benches, write test plans, specify coverage, write tests, and debug across simulation, emulation, formal verification, and silicon validation.

Office-based with four days in the office per week, one day remote as needed. The role requires 5+ years in ASIC verification, strong SystemVerilog/UVM, and a track record from concept to mass