Senior ASIC Verification Engineer for AI & HPC

NVIDIA Corporation; Massachusetts; Sur place; USD 168 000 - 265 000; Plein temps

Avantages offerts par ce poste

Equity

Résumé du poste

NVIDIA is seeking a Senior Design Verification Engineer to verify the design and implementation of the next generation of High Speed I/O controllers for the world’s leading SOCs and GPUs. This role offers the opportunity to impact products ranging from consumer graphics to AI and autonomous driving platforms.

You will apply SystemVerilog/UVM-based verification to IP/sub-system levels, build reusable verification components, and collaborate with architects, designers, and silicon teams to ensure

Qualifications

• 5+ years of relevant experience.
• Experience at unit/sub-system/SOC level with SystemVerilog and UVM.
• Expertise in verification of IP or interconnect protocols (Ethernet, USB, SATA).
• Familiarity with random stimulus, coverage-driven verification, and assertion-based verification (UVM).
• Strong debugging, analytical, and problem-solving skills.

Responsabilités

• Verify ASIC design, architecture, golden models and micro-architecture of HSIO controllers at IP/sub-system levels using UVM.
• Build reusable bus functional models, monitors, checkers and scoreboards following coverage-driven verification.
• Define verification scope, develop test plans, tests, and verification infrastructure to verify design correctness.
• Collaborate with architects, designers, and pre/post-silicon verification teams.

Connaissances

SystemVerilog

UVM

Verification methods

Formation

Bachelor's/Master's degree

Description du poste

NVIDIA is seeking a Senior Design Verification Engineer to verify the design and implementation of the next generation of High Speed I/O controllers for the world’s leading SOCs and GPUs. This role offers the opportunity to impact products ranging from consumer graphics to AI and autonomous driving platforms.

You will apply SystemVerilog/UVM-based verification to IP/sub-system levels, build reusable verification components, and collaborate with architects, designers, and silicon teams to ensure