Senior ASIC Verification Engineer – AI-Driven UVM & SV

Micron Technology; Minneapolis (MN); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical plans

Paid time off

Paid holidays

Job summary

Micron Technology is seeking a Senior ASIC Design Verification Engineer in Minnesota to own verification environments for SOCs, collaborating with design and post-silicon teams, and driving coverage closure. You will develop UVM-based verification, Python testbenches, and explore AI-assisted approaches to improve productivity and quality.

The role requires 3+ years in IP/SoC verification, strong SystemVerilog and Python skills, and excellent problem-solving and communication abilities in a

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering or equivalent.
• 3+ years of proven experience in IP or SoC verification.
• Hands-on experience with UVM and constrained-random verification.
• Strong proficiency in SystemVerilog and Python.
• Proven analytical, debugging, and communication skills.

Responsibilities

• ASIC/FPGA design verification experience with UVM methodologies.
• Develop and maintain UVM-based SystemVerilog verification environments.
• Build and enhance Python-based testbenches and simulation infrastructure.
• Define and execute block and system-level verification plans.
• Debug complex functional and integration issues in close collaboration with design teams.
• Drive coverage closure and continuously improve verification quality metrics.
• Explore and adopt AI-assisted techniques and tools to improve verification productivity and debug efficiency.
• Excellent problem-solving skills.
• Phenomenal teammate with excellent interpersonal communication skills.

Skills

UVM methodologies

SystemVerilog

Python

Verification planning

Debugging

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering or equivalent

Tools

UVM

SystemVerilog

Python

Job description

Micron Technology is seeking a Senior ASIC Design Verification Engineer in Minnesota to own verification environments for SOCs, collaborating with design and post-silicon teams, and driving coverage closure. You will develop UVM-based verification, Python testbenches, and explore AI-assisted approaches to improve productivity and quality.

The role requires 3+ years in IP/SoC verification, strong SystemVerilog and Python skills, and excellent problem-solving and communication abilities in a