Senior ASIC Verification Engineer — AI-Driven Debug & UVM

Micron Technology, Inc; Minneapolis, Northern (MN, KY); Hybrid; USD 120,000 - 150,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. is seeking a Senior ASIC Design Verification Engineer to own end-to-end verification environments for next-generation SOCs.

You will collaborate with verification, design, and post-silicon validation teams to deliver high-quality results and explore AI-assisted techniques to enhance productivity and debugging efficiency. Typical responsibilities include developing new simulation environments, executing verification plans, and debugging complex issues.

Qualifications

• Bachelor’s or Master’s degree in EE/CE or equivalent.
• 3+ years of proven IP/SoC verification experience.
• Hands-on with UVM and constrained-random verification.
• Strong SystemVerilog and Python skills.
• Excellent analytical, debugging, and communication skills.

Responsibilities

• ASIC/FPGA design verification experience with UVM methodologies.
• Develop and maintain UVM-based SystemVerilog verification environments.
• Build and enhance Python-based testbenches and simulation infrastructure.
• Define and execute block and system-level verification plans.
• Debug complex functional and integration issues in close collaboration with design teams.
• Drive coverage closure and continuously improve verification quality metrics.
• Explore and adopt AI-assisted techniques and tools to improve verification productivity and debug efficiency.
• Excellent problem-solving skills.
• Phenomenal teammate with excellent interpersonal communication skills.

Skills

Analytical thinking

Communication

Team collaboration

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering or equivalent

Tools

UVM

SystemVerilog

Python

Constrained-random verification

Regression testing

Job description

Micron Technology, Inc. is seeking a Senior ASIC Design Verification Engineer to own end-to-end verification environments for next-generation SOCs.

You will collaborate with verification, design, and post-silicon validation teams to deliver high-quality results and explore AI-assisted techniques to enhance productivity and debugging efficiency. Typical responsibilities include developing new simulation environments, executing verification plans, and debugging complex issues.