ASIC Design Verification Engineer: AI‑Enhanced Debug & UVM

Micron Technology, Inc; Minneapolis, Northern (MN, KY); Hybrid; USD 90,000 - 130,000; Full time

Job summary

Micron Technology, Inc. is seeking an ASIC Design Verification Engineer to join our world-class verification team in Minnesota.

You will develop verification components for complex SOCs, build UVM-based environments, and drive coverage closure while collaborating with design teams to ensure on-time delivery and quality. The role requires 2+ years in IP/SoC verification, strong SystemVerilog and Python skills, hands-on UVM and constrained-random verification, and excellent problem-solving and

Qualifications

• 2+ years of proven experience in IP or SoC verification.
• Hands-on experience with UVM and constrained-random verification.
• Strong proficiency in SystemVerilog and Python.
• Proven analytical, debugging, and communication skills.

Responsibilities

• ASIC/FPGA design verification experience with UVM methodologies.
• Develop and maintain UVM-based SystemVerilog verification environments.
• Build and enhance Python-based testbenches and simulation infrastructure.
• Execute block and/or system-level verification plans.
• Debug complex functional and integration issues in close collaboration with design teams.
• Drive coverage closure and continuously improve verification quality metrics.
• Explore and adopt AI-assisted techniques and tools to improve verification productivity and debug efficiency.
• Excellent problem-solving skills.
• Phenomenal teammate with excellent interpersonal communication skills.

Skills

UVM methodology

SystemVerilog

Python

Constrained-random verification

Debugging

Communication skills

IP/SoC verification

Education

Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering

Tools

UVM framework

Job description

Micron Technology, Inc. is seeking an ASIC Design Verification Engineer to join our world-class verification team in Minnesota.

You will develop verification components for complex SOCs, build UVM-based environments, and drive coverage closure while collaborating with design teams to ensure on-time delivery and quality. The role requires 2+ years in IP/SoC verification, strong SystemVerilog and Python skills, hands-on UVM and constrained-random verification, and excellent problem-solving and