Senior ASIC Verification Engineer: UVM, SystemVerilog

Micron Technology, Inc; Minneapolis (MN); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical, dental, vision plans

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. invites a Senior ASIC Design Verification Engineer to join its ASIC Verification team in Minnesota. You will own verification environments end-to-end for complex SOCs, collaborating with design and post-silicon teams, and driving high-quality verification plans.

You will leverage UVM, SystemVerilog, and Python, with opportunities to apply AI-assisted techniques. The role emphasizes constrained random verification, debugging, and strong communication.

Qualifications

• Bachelor’s or Master’s degree in Electrical or Computer Engineering or equivalent.
• 3+ years of IP or SoC verification experience.
• Hands-on with UVM and constrained-random verification.
• Strong SystemVerilog and Python skills.
• Good analytical, debugging, and communication abilities.

Responsibilities

• Develop and maintain UVM-based SystemVerilog verification environments.
• Build and enhance Python-based testbenches and simulation infra.
• Define and execute block and system-level verification plans.
• Debug complex functional and integration issues with design teams.
• Drive coverage closure and improve verification quality metrics.
• Explore AI-assisted techniques to boost productivity and debugging efficiency.
• Collaborate closely with verification, design, and post-silicon teams.
• Demonstrate excellent problem-solving and teamwork.

Skills

UVM verification

SystemVerilog

Python

Verification plans

Debugging

AI-assisted methods

Problem solving

Team communication

IP/SoC verification

Education

BSc/MSc EE or CE

Tools

UVM

SystemVerilog

Python

Job description

Micron Technology, Inc. invites a Senior ASIC Design Verification Engineer to join its ASIC Verification team in Minnesota. You will own verification environments end-to-end for complex SOCs, collaborating with design and post-silicon teams, and driving high-quality verification plans.

You will leverage UVM, SystemVerilog, and Python, with opportunities to apply AI-assisted techniques. The role emphasizes constrained random verification, debugging, and strong communication.